We’re all aware of the negative impact the market has had on business over the last 18 months. Doing more with less and guessing which way the market is heading are not new concepts, but certainly more challenging given the overall market instability. Technology companies have been going through continuous reorganizations to optimize their organization size, skill sets, and intellectual property (IP) portfolio. Finding the right balance of these components can make the difference between success and failure.
To win in the highly-competitive consumer electronics market in particular, both system and semiconductor companies need to focus on the unique value they can offer. Smaller design teams are the new reality, so the ability to maximize the output of these limited resources will clearly separate you from the pack. Part of the overall success strategy is correctly identifying technology in which to invest your critical engineering resources versus the technology that can be outsourced, especially as technology becomes standard. Licensing standalone IP blocks for integration into an overall system design is reasonably easy to justify. Some obvious examples are USB, PCI, and memory-controller blocks.
Perhaps another obvious, but not so straight-forward example is outsourcing of the core processor. Most of today’s companies do outsource processor cores, but it took a long time to come to the conclusion that breaking away from an internal architecture was the right strategy. And this is with good reason. Many internal processors were optimized for a specific application (the lowest power or the best performance for a given benchmark). As the power/performance gap closed, however, it was becoming difficult to justify the differentiated value given the expense of maintaining your own instruction set and support tools. Not to mention that OEMs were no longer willing to commit their growing software investment to a specific company’s hardware architecture.
Now with the rapid advance of process technology, the ability to squeeze more capability into a single system-on-chip (SoC) is forcing semiconductor developers to look at IP from outside sources. Most new design starts are targeting a 45-nm process, which means an embedded SoC can easily have 50 or even 100 cores. Clearly no one company, except for some of the very largest, can develop all the technology blocks needed in these complex devices. Because it’s clear most companies need to outsource non-critical IP blocks, a new set of tasks and questions are then required by the design teams. How reliable is the outsourced IP? Will it work easily with other parts of the system? Does it support standards? How easily can it be reused, and will it work in our tools flow? Sometimes the energy spent dealing with these questions can be as much work as developing the IP yourself (although the skill set will be different).
Ideally, when a product is outsourced, design managers don’t want to spend their resources developing bridges to interface to the IP or modify their tool flow to maintain all the features they have come to rely on. There are efforts from both IP and EDA companies to create more unified environments that allow the mixing and matching of tools and IP so that they work together seamlessly. These are necessary efforts and good progress is being made. For example, IP-XACT was developed as standard description for IP blocks and the Catalyst program from Synopsys is bringing tool and IP vendors together. But what is the next big outsourcing trend in SoC development? What is the technology piece that is becoming difficult and too costly to maintain internally?
The increasing number of heterogeneous SoC cores and increasing chip speed mean connecting these cores is no longer an easy task. What was once thought of as a simple bus now requires the sophistication to manage complex data flow through the system, the ability to connect many IP cores together from different sources with different protocols, and even the ability to communicate with the system software. Intelligent on-chip networks are becoming a standard way to deal with these issues. The term “network” is no longer an analogy. These are real networks that have to connect many blocks using multiple connection topologies to support the various types of data, including switches, routers, and serial and parallel connections. Developing these components is no longer the task of a single engineer on the design team, but instead requires a serious technology investment.
The on-chip network makes the goal of connecting any IP from any source a reality because it has to interface with all the different types of cores in the system. The network handles protocol conversions, making them transparent to the SoC design team. This will speed chip development and allow the IP to be reused in other designs. Since the on-chip network is now treated as a major IP block in the system with a universal interface, it allows cores to be added or removed with very low risk to the system. Also, the on-chip network is a fully verified IP block, reducing debug effort and therefore development time.
The on-chip network is sitting at the heart of the SoC and it “sees” all the data flow through the system, allowing for advanced data flow management and data services. Connections for high-speed cores that need deterministic access to memory are managed right along with slower peripherals. Advanced data-flow-services can also be added to the system, including quality of service, secure memory regions, and error handling. Finally, having a centralized network also facilitates advanced power management since there is now a communications mechanism to control each power region.
Given where the market is today and where it’s heading, clearly outsourcing of the on-chip network makes good business sense. Designers can treat the entire on-chip network as a single, highly configurable IP block. On the other hand, developing and maintaining a competitive product without using outsourced IP takes a sizeable design team—something that’s not practical for most companies, particularly now. Even in a strong market, there’s an advantage to outsourcing the on-chip network because it will free your critical engineering resources to focus on your company’s particular value-added functions. Plus, having an intelligent network at the center of the SoC design speeds development time: dealing with multiple IP becomes easier, the reuse of your IP becomes easier, and you can take full advantage of the advanced feature set to improve the overall performance of your SoC.
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