Historically, the speed and complexity of electronic circuits required for manufacturing has out-matched the interconnects used to join circuits together. A first approximation of interconnect performance controls are:
- Power consumption (capacitance, voltage, frequency)
- Signal speed (resistance, inductance, capacitance)
- Signal integrity (inductance, capacitance)
Various strategies have been devised to address these controls. For example, materials and process innovations have lead to copper tracks and low-k dielectrics, while novel circuit designs have given rise to the 64-bit-wide bus, multi-data transfers per clock cycle, and synchronous clock technologies.
However, the performance of each interconnect is fundamentally dictated by its length, width, and thickness. Device integration solutions like system-on-a-chip (SoC) and 3D stacking are intended to directly address these controls. In the case of 3D stacking, the objective is to replace the long, horizontal, wiring traces that become necessary when die are placed side-by-side with short, vertical pathways, concomitantly reducing the three fundamental controls of resistance, inductance, and capacitance.
Making vertical interconnects generally requires some form of through-silicon via (TSV) technology. TSVs are conceptually very simple to produce and many variations exist. A common implementation is a hollow pipe with near-vertical sidewalls, machined through the thickness of the silicon. A dielectric film overlaid with conductive metal is applied to the sidewalls of the pipe. Generally, TSVs furnish electrical pathways between bond pads on one face of the die and lands on the opposing face (Fig. 1).
TSVs aren’t new; they have been used on commercial products since 1976. All GaAs die with coplanar RF circuits use through vias to provide grounding points. However, despite many years of work, TSVs have failed to achieve widespread adoption. There are several reasons for this, including the high cost of the wafer-scale equipment required, the slow etch rate of silicon that curtails throughput, and the complexity of the additional process steps to fabricate conductive pipes that are insulated from the silicon through which they pass.
Furthermore, issues of reliability have yet to be satisfactorily solved. Points of weaknesses in the design include dielectric and conductive coating of the side walls of a high aspect ratio pipe, and the 90 degree bends at the top and base of the pipe that the redistribution layer must traverse and maintain connectivity during thermal cycling. There’s also the issue of cleaning the back of the bond pad so that the redistribution layer can make an ohmic contact to it.
Developing a TSV technology that addresses all of the above problems remains elusive. However, by focusing on special-case conditions, it’s possible to realize TSV solutions that meet all three requirements for commercial success, namely adequate functionality, low cost, and proven reliability. An example is wafer-level packages for solid-state image sensors.
WLPS FOR SOLID-STATE IMAGE SENSORS
Typically, more than two billion image sensors are produced each year. These are primarily incorporated in portable electronics products such as camera-enabled cell phones, digital still cameras and increasingly, laptop and netbook computers. Like most other semiconductor devices, solid state image sensors require some form of enclosure to ensure longevity. Traditionally, this was achieved using chip-on-board (COB) assembly processes, but the industry is now transitioning to wafer-level packaging (WLP).
A wafer-level cavity package for an image sensor is achieved simply by applying a picture frame of adhesive around each die, attaching a glass wafer, and then sawing the assembly to yield individual die, each with a cover over the delicate image sensor area (Fig. 2).
WLP has great economic value for image sensors. In WLP, the die are packaged in the wafer while still in wafer form and the wafer is then singulated to free individually packaged die. Thus, the costs of packaging are shared among the good die on the wafer, greatly reducing packaging costs per die. With typically between 750 and 1250 die on a 200-mm-diameter image sensor wafer, this results in an order of magnitude decrease in the packaging time and cost per die, compared with COB assembly.
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