Surely, designers of ASICs and application-specific standard parts (ASSPs) using cell-based methods need sophisticated tools to get the job done. Yet ASIC/ASSP designers still rely on the old EDA workhorses—logic synthesis, simulation, and place and route. Such tools are intimately tied to standard cell intimately tied to standard cell libraries, which contain basic predefined logical building blocks, or cells. Standard cells present a "one-size-fits-all" design environment, limiting the quality of designs. This is a key contributor to a growing gap between full-custom and ASIC design performance. While large, full-custom designs are approaching 3-GHz clock speeds, getting an ASIC to work at 500 MHz at the same process node is a bear.
Physical synthesis has eased the timing closure crunch between logic synthesis and place and route. Meanwhile, other design challenges have emerged. Signal integrity and power are major issues at the 0.13-µm (130-nm) process node. Existing synthesis tools map a given design to relatively small cells found in a predefined library. While tried and true, this methodology results in designs with too many cells and uncharacterized interconnects between them, both of which are obstacles to signal integrity and power optimization.
AUTOMATION IS KEY Clearly, a full-custom design methodology is different from that of an ASIC/ASSP. However, to better harness the potential of nanometer IC fabrication processes, an increasing number of optimization techniques used in custom design must be automated and incorporated into cell-based design flows.
Hybrid optimization will enable this process by transparently optimizing a given cell-based design at the logic level and at the transistor level, taking into account key physical design issues like placement and routing. By definition, hybrid optimization is automated and context-specific, or localized. It operates smoothly across the gate/cell level and the transistor level of abstraction, and is driven by the results of global analysis and operations—for example, static timing analysis (STA), buffering, sizing, and placement and routing. Thus, designers can create with reduced numbers of cells, transistors, and wires.
DIVIDE AND CONQUER Two crucial capabilities serve as the key to hybrid optimization—automated identification of regions in the design that are best suited for custom design optimization, and automated optimization of the logic in those regions. The first capability, termed clustering, is based primarily on analysis of the placed-gate/cell-level view of a design. The second capability, termed mapping, relies primarily on the transistor-level manipulation of circuitry to realize the functionality of a given cluster. Each unique cluster identified during hybrid optimization is implemented as a design- and context-specific standard cell. These cells tend to be larger than typical standard cells found in cell libraries, but significantly smaller than handcrafted macrocells often used by designers when all else fails.
New EDA tools that fully harness the potential of existing and future IC fabrication processes are inevitable. Hybrid optimization lays the foundation for a digital-IC design methodology that encompasses transistor-level manipulation of a design from within automated cell-based digital design flows.
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