[Technology Report]
Reconfgurable Architectures Chart A New Course For DSPs
The latest crop of DSP cores promises flexibility to cope with the changing requirements of evolving third- and fourth-generation wireless standards.
Ever-increasing computational complexity and evolving wireless and consumer standards are forcing developers of monolithic digital signal processing (DSP) chips to look beyond the traditional fixed architectures that have served the industry adequately for over a quarter of a century. While the fixed architectures continue to progress in capability, the MIPS and MOPS appetite of the emerging 3G and 4G wireless applications is soaring faster than Moore's Law.
Hence, as conventional fixed DSPs run out of steam, they're being combined with expensive application-specific ICs (ASICs) to supply the additional processing horsepower needed. Also, in many cases, multiple fixed DSP cores are being packed in parallel on one chip to address the huge processing requirements of these applications. Besides adding further cost and consuming more power, these parallel processing chips are difficult to program.
To overcome these limitations and offer a flexible, cost-effective solution, many new entrants to the DSP market are extolling the virtues of configurable and reconfigurable DSP designs. This latest breed of DSP architectures promises greater flexibility to quickly adapt to numerous and fast-changing standards. Plus, they claim to achieve higher performance without adding silicon area, cost, design time, or power consumption. In essence, because the architecture isn't rigid, the reconfigurable DSP lets the developer tailor the hardware for a specific task, achieving the right size and cost for the target application. Moreover, the same platform can be reused for other applications.
Because development tools are a critical part of this solution—in fact, they're true enablers—the newcomers also ensure that the tools are robust and tightly linked to the devices' flexible architectures. While providing an intuitive, integrated development environment for the designers, the manufacturers ensure affordability as well.
Reconfiguring The Architecture: Some of the new configurable DSP architectures are reconfigurable too—that is, developers can modify their landscape on the fly, depending on the incoming data stream. This capability permits dynamic reconfigurability of the architecture as demanded by the application. Proponents of such chips are proclaiming an era of "chip-on-demand," wherein new algorithms can be accommodated on-chip in real time via software. This eliminates the cumbersome job of fitting the latest algorithms and protocols into existing rigid hardware.
Toward that end, Chameleon Systems had developed a reconfigurable communications processor (RCP) that could be reconfigured for different processing algorithms in one clock cycle. But a softening in the 3G marketplace, combined with the difficulty of using new tools and programming a new architecture, forced Chameleon to rethink its reconfigurable DSP strategy.
Chameleon designers are revising the architecture to create a chip that can address a much broader range of applications. Plus, the supplier is preparing a new, more user-friendly suite of tools for traditional DSP designers. Thus, the company is dropping the term reconfigurability for the new architecture and going with a more traditional name, the streaming data processor (SDP).
Though the SDP will include a reconfigurable processing fabric, it will be substantially altered, the company says. Unlike the older RCP, the new chip won't have the ARM RISC core, and it will support a much higher clock rate. Additionally, it will be implemented in a 0.13-µm CMOS process to meet the signal processing needs of a much broader market. Further details await the release of SDP sometime in the first quarter of 2003.
While Chameleon is in the redesign mode, QuickSilver Technologies is in the test mode. This reconfigurable proponent, which prefers to call its architecture an adaptive computing machine or ACM, has realized its first silicon test chip. According to vice president of marketing John Watson, the chip demonstrates that the ACM hardware can adapt dynamically to the software.
In fact, the tests indicate that it outperforms a hardwired, fixed-function ASIC in processing compute-intensive cdma2000 algorithms, like system acquisition, rake finger, and set maintenance. For example, the ASIC's nominal speed for searching 215 phase offsets in a basic multipath search algorithm is 3.4 seconds. The ACM test chip took just one second at a 25-MHz clock speed to perform the same number of searches in a cdma2000 handset. Likewise, the device accomplishes over 57,000 adaptations per second in rake-finger operation to cycle through all operations in this application every 52 µs (Fig. 1). In the set-maintenance application, the chip is almost three times faster than an ASIC, claims QuickSilver.
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