[Design View / Design Solution]
Troubleshoot High-Speed Buses By Clearing "Clock Scheme Fog"
Understand how double-pumped, quad-pumped, and source-synchronous devices work, and you can capture the right data at the right time.
High-speed digital buses continuously evolve. Not only are they faster, but they're chang-ing how a system clocks data. To improve data throughput, emerging synchronous digital buses are sending data multiple times per cycle via an array of clocking schemes. High-speed synchronous data transfers are becoming more common: Synchronous clocking modes that began life in high-end computing equipment are now trickling down to mid-market products. Thus, there's a greater demand for labor-saving digital troubleshooting solutions.
One of the most productive tools for debugging synchronous systems is the logic analyzer. When properly equipped, it can directly capture high-speed synchronous data. At the heart of the high-speed synchronous data-acquisition challenge, though, is the requirement for great flexibility in clocking and triggering.
Digital system designers have learned that in conventional parallel-bus architectures, brute-force increases in clock rate can yield diminishing returns. In response to this lesson, digital architects have devised a number of innovative clocking approaches, including "double-pumped," "quad-pumped," and "source-synchronous." This article defines and explains how these different approaches work and how to capture the right data at the right time.
One approach that gets particular focus is source-synchronous. Here, dedicated strobe signals are used instead of, or sometimes in addition to, a normal clock pulse. This makes acquisition inherently more complex. Yet despite the fact that several more steps are involved in its setup, as opposed to the other approaches, a dedicated source-synchronous mode makes the setup process straightforward. The "pyramid" step approach is detailed in the article.
HIGHLIGHTS:
New Clocking Scheme
"Double-pumped", "quad-pumped," and "source synchronous" are three clocking approaches created as an alternative to brute-force clock-rate increases.
Special Acquisition Modes
Today's logic analyzers must be able to handle the many edge and data combinations. One proven method is to pair high sample rates with multiplexing techniques. This "doubling" known as 2X clocking, enables capturing of signals with narrow edge spacing.
Source-Synchronous Acquisiton
Source synchronous clocking uses dedicated strobe signals instead of, or with, a normal clock pulse. Most logic analyzers require external interfaces to pre-process source-synchronous acquisitions, while some have the ability built in.
Source-Synchronous Pyramid
Though it has several more steps than other approaches, a dedicated source-synchronous mode makes setup straightforward. Discussed are the successive layers of configuration choices that form the setup "pyramid."
Table: Synchronous Operation Types
Various types of synchronous operation currently in use are broken down for comparison. The edge and data combinations mentioned in "Special Acquisition Modes" are listed here.
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