[Technology Report]
Optimized Processor Blocks Eliminate The Gamble With RISC For SoC Designs
The latest RISC CPUs, DSP cores, and software- definable processors give designers easy-to-integrate blocks that deliver top-notch performance.
The ability to implement a system-on-a-chip has kept getting easier year after year. Those chips often house at least one CPU, and in many cases, a companion digital-signal processor. Until recently, though, the CPUs and DSP blocks that designers had available were somewhat rigid. Their feature sets were fixed, and they usually had a predetermined physical layout. That layout enabled the core providers to guarantee the processor's performance. But it kept system-on-a-chip (SoC) designers from really optimizing the chip layout. Fixed-size and -shape blocks cause restrictions on the rest of the chip's topology.
It's a new world now. The latest core releases have been optimized for SoC designs. Many are still available in "hard" form, with the physical layout predefined. But an increasing percentage come in synthesizable form, which lets the SoC designer control the implementation. The burden then falls on the designer or the synthesis tools to do the best job possible in implementing the core. The synthesized core's performance, or clock speed, can often be 10% to 50% slower than the core supplier's optimized version.
The choice facing designers is quite broad. Basic CPU cores are available in word sizes ranging from 4 to 64 bits. In the DSP arena, 16-bit engines are the most popular. Straddling the processor and DSP worlds are some merged CPU/DSP engines, along with most of the recently released very-long-instruction-word (VLIW) processor cores.
Memories And Peripherals Also Of course, a CPU or DSP core doesn't stand alone. Many companies provide fixed or compilable memory blocks that can be used for on-chip caches or other blocks. Plus, a lot of intellectual-property (IP) suppliers can deliver the peripheral functions for the desired I/O interfaces and control functions.
Along with those processors, memory, and I/O functions, the on-chip bus that interconnects all of the blocks has grown very crucial. As the operating speed of all the blocks increases, the speed at which data can move from block to block is rapidly becoming a performance-limiting factor.
The bus must be robust enough to tie into a wide variety of IP blocks with little to no additional logic. It then becomes the "universal on-chip backplane" to which all of the IP blocks can be tied.
Many large suppliers of application-specific ICs (ASICs) and application-specific standard products (ASSPs) have developed just such bus structures. Companies like IBM, LSI Logic, Motorola, Philips, and others offer silicon backplanes that are either developed in house or based on licensed IP.
To connect gluelessly to the bus, for example, both IBM and Motorola have independently developed on-chip buses and specifications. They've defined how third-party-designed blocks can be implemented. IBM's approach, dubbed CoreConnect, works with the superscalar PowerPC 440 core. System designers can craft SoC systems with a processor that hits 720-MIPS when clocked at 400 MHz. Its bus models and IP are available for licensing. Information can be found on the web site: www. ibm.com/microelectronics.
Like most other ASIC suppliers, LSI Logic spent much of its past crafting proprietary on-chip buses. The company is now taking an industry-standard approach, however, focusing on using the latest version of the advanced-microcontroller bus-architecture (AMBA) interface. Advanced RISC Machines (ARM) designed AMBA as the main core interface and coprocessor interconnect structure for its own family of ARM RISC processor cores.
Currently, close to 30 companies have licensed the ARM and AMBA interfaces, making AMBA one of the most widely used interfaces. LSI Logic is busy unifying all of the bus interfaces on the processor cores and high-end peripheral products that it offers, such as MIPS, ZSP, and ARM. By offering AMBA interfaces, it speeds system design. The company also hopes to leverage any IP developed by other ARM suppliers. It will simply be "bolted" onto the AMBA interface.
Two Buses Defined The AMBA 2.0 interface specification actually defines two buses. The high-speed processor interface is referred to as the advanced high-performance bus (AHB). The second, slower interface targets peripheral support. It's called the advanced peripheral bus (APB).
Both buses are single-edge clocked and they multiplex the address and data lines. But the AHB interface can be defined with bus widths as large as 1024 bits. It also will support up to 16 masters. The bus boasts a split-transaction protocol and a burst-access mode with programmable-block sizes.
Other players are offering alternative bus standards. Sonics Inc., Mountain View, Calif. (www.sonicsinc.com), has crafted a silicon backplane that can be used with IP from multiple sources. It allows data transfers of 640 Mbytes/s when clocked at 80 MHz. A guaranteed latency ensures that real-time deadlines can be met. (See "Tool Suite Is Strong Medicine For SoC Design Headaches," electronic design, Sept. 7, 1999, p. 37).
For the last couple of years, the Virtual Socket Interface Alliance, Los Gatos, Calif. (www.vsi.org), has been working on a silicon backplane bus-interface standard. Earlier this year, the committee released the first version, on-chip bus version 2, rev. 1.0 (OCB 2 1.0). It defines a standard virtual-component interface (VCI) for both IP suppliers and system-chip designers/integrators.
The group actually defined an interface signal set and a simple logic "wrapper." The wrapper can be designed to make any peripheral or add-on circuit functions compatible with the VCI standard. In the latest version of the on-chip bus specification, VCI-compatible virtual cores can operate with on-chip buses of varying protocols and performance levels.
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