Deftly optimizing ASIC critical paths, this tool rides atop existing cell-based flows to improve timing while leaving physical design largely undisturbed.
Timing closure for ASIC design has always been difficult to achieve. But as IC process geometries fall below the nanometer threshold, the shortfalls in timing are growing larger. Timing closure tools that resize and buffer critical paths don't make up the difference. Traditional techniques can lead to months of fruitlessly chasing a timing goal. What's required is a new approach to timing closure, one that goes beyond the currently fashionable melding of logic synthesis and physical design as exemplified by physical synthesis.
Missing from that equation is optimization at the transistor level. In its first product, ZenTime, Zenasis Technologies has devised a tool that uses what it terms hybrid optimization technology. The tool operates simultaneously at the transistor, gate, and physical levels to achieve a fundamental improvement in timing. It does so while permitting the design team to use its existing cell-based design flow and without imposing a power, area, or signal-integrity penalty.
ZenTime starts with a synthesized gate-level netlist, with or without placement information, and the design constraints in the form of a PrimeTime SDC file.
First, the tool analyzes the design to identify critical timing regions and paths. It does this via a built-in static timing analysis (STA) engine designed to emulate Synopsys' PrimeTime static timing analyzer. In fact, timing correlation between PrimeTime and ZenTime's STA engine has been found to be high. "The timing engine walks through critical regions of the design, where it finds small cell groups that, if improved, overall timing of all critical paths would improve," says Debashis Bhattacharya, Zenasis' chief technology officer.
The tool identifies key clusters of gate-level logic that can be optimized at the transistor level to achieve the desired timing goals. These clusters are ranked and prioritized by the STA engine.
Once clusters are identified, ZenTime creates new cells by remapping the clusters' function at the transistor level. These new cells, called ZenCells, are custom-crafted in the context of the design and on the fly.
ZenCells are faster than the clusters they replace for several reasons, Bhattacharya notes. "In some cases, completely new functions are created that cannot be found in any fixed-cell library," he explains. They incorporate context-specific stack ordering and custom transistor sizing. They also benefit from transistor topology exploration that the tool performs before settling on an optimal inter-cell topology.
A comparison of a sample path from a customer design before and after optimization shows how ZenCells can break timing bottlenecks in critical paths (Fig. 1). The comparison also shows how new functions are created in ZenCells. In the optimized critical path, the multiplexer and NAND gate were combined into ZenCell 2 with a resultant delay of less than the multiplexer alone. Additionally, Bhattacharya notes, "No library we've seen to date has this function as a standard cell."
Through its insertion of context-specific crafted ZenCells, ZenTime can wield dramatic impact on global timing. In another customer example, a block of 30 kgates saw an overall tightening of slack distribution while gaining some 70 MHz of performance, from an initial frequency of 562 MHz to a final frequency of 630 MHz (Fig. 2).
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