[Design View / Design Solution]
Silicon-On-Insulator Technology Bumps Up SoC Performance
By employing the proper models, designers can fully understand SOI transistor behavior and come up with successful circuit designs.
As the semiconductor industry shifts to 0.13-µm and smaller devices, IC designers must strongly consider materials issues.
The substrate material upon which chips are built can profoundly affect design structures, interconnects, and other critical design considerations, particularly when advanced circuit materials, such as copper and low-k, are used in device manufacturing.
Innovative enhancements supporting silicon-on-insulator (SOI) have made SOI attractive for next-generation systems-on-a-chip (SoCs). But to get the full benefits from SOI, the industry must optimize SOI design processes and methodologies.
SOI improves device speed by 15% to 35% over that exhibited by bulk CMOS technology. This speed upgrade represents two years of bulk CMOS advances. A lower threshold, reduced junction leakage (when compared with bulk CMOS), and low junction capacitance give chip makers the tools to master standby current and reduce device power consumption by more than half.
Getting the most out of SOI's benefits, whether fully or partially depleted, requires knowledge of the how the SOI material behaves. At this point, the article goes into depth on Spice modeling of SOI circuits. In particular, the contrast between using fully and partially depleted devices in Spice simulation is highlighted. The article states that standard bulk models can be used if key parameters are modified, but ultimately an accurate circuit simulation can't be achieved. On the other hand, the electrical behavior of partially depleted devices is similar to bulk devices, therefore they can be modeled identically.
Developing a library for an SOI design kit is another key point addressed. SOI design kits aren't currently available, so library requirements are provided here.
HIGHLIGHTS:
SOI Simulation Challenges
To get an optimized SOI circuit design, an SOI model is needed to help the designer understand the SOI transistor's behavior. Such models must be implemented in a Spice circuit. Several SOI models currently reside in commercial Spice simulators.
Fully Depleted SOI Simulation
Though not completely accurate, a Spice simulation of SOI circuits using fully depleted devices can be performed using a standard bulk model if key parameters like junction capacitance and current, as well as threshold voltage are modified.
SOI Design Kit Requirements
Unlike bulk CMOS, design kits for SOI aren't currently available. ASIC design requires a design kit composed of a library of standard cells, I/Os, and RAM and ROM compilers. Developing a library requires an established characterization methodology.
Sidebar: Smart-Cut Process
SmartCut technology uses ion implantation and wafer bonding to make the UNIBOND SOI wafers. Hydrogen ion implementation acts as an atomic scalpel, enabling thin slices of monocrystalline film to be cut from a donor wafer.
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