[Product Innovation]
10-Gbit/s Ethernet Switch Chip Set Serves Up Advanced QoS At Wire Speed
Smart packet processor performs core and MAN switching/routing functions and supports layer-3 MPLS features.
Switching systems continue to be called on to deliver higher packet throughputs and higher quality-of-service levels. Switching circuits controlling the data flow must perform more and more packet analysis and routing functions at wire speeds. Delays associated with performing the analysis can't be tolerated, as many media-rich files the network must now transport are time-dependent.
Developed by Marvell Semiconductor, the Prestera chip set is taking on the challenge of handling data streams at 10 Gbits/s and offering system scalability and high levels of quality-of-service (QoS). It supports layers 2 through 5 of the International Standards Organization's Open Systems Interconnect reference model, multiprotocol label switching (MPLS), and many other advanced features. The Prestera packet processor and supporting chips in the chip set deliver the first switching architecture to simultaneously perform processing for layers 2, 3, and 4, and MPLS network address translation (NAT) and load-balancing at 10-Gbit/s data rates.
In contrast, the best current competitive solutions only perform processing for layer 2 (L2) at 10 Gbits/s, or use highly flexible and programmable network processors that perform L2 through L4 at 2.5 Gbits/s. The chip set also has the flexibility to address the requirements of Enterprise as well as core and metropolitan area networks (MANs). That enables OEMs to address multiterabit architecture scalability versus competitive standalone solutions. Additionally, this solution offers a single software and hardware architecture for 10-Gbit Ethernet, 1-Gbit Ethernet, and Fast Ethernet, letting OEMs address high-end to low-end solutions from multiterabit-class switches and routers to simple desktop switches.
Scaling Back The chip set can be scaled to handle the terabit data flows needed to serve the large MANs and more moderate hundreds of gigabits per second flowing in Enterprise-class systems. The Marvell Prestera switching architecture is broken into a three-chip solution for the typical line card, and another chip that would be used to form the high-level switch fabric.
The main chip that handles all packet data is the Prestera packet processor. On this chip, designers at Marvell have implemented all the packet buffering, transmit and receive memories and queuing engines, a flow classifier, packet and protocol processing, a 15-Gbit/s expansion bus, and a 10-Gbit/s media access controller (Fig. 1).
The ingress control pipe is a high-performance multistage pipeline designed to make packet-processing decisions at full wire speed for all incoming packets. Some of the processing and decision making that happens within this block includes layer 2 switching and all 802.1D/Q bridging functions, including support of link aggregation groups per 802.3ad and various 802.1 control protocols, layer-3 IPv4 unicast/multicast forwarding, and multi-field flow classification to classify up past layer 5 at full-wire speed. The results of this classification then affect stages of the pipeline responsible for CoS marking, NAT, filtering, and policy-based routing/switching. The block also performs traffic conditioning, which is responsible for Policing, Re-Marking CoS, Billing, MPLS switching, and a wide variety of security mechanisms that operate at L2, L3, and MPLS.
There will initially be four versions of this chip; two targeted at MAN/core applications for the highest-performance systems, and two targeted at Enterprise-class systems. Each pair of circuits is further differentiated. One version contains a single 10-Gbit port to access the network, while the other contains 10 1-Gbit ports, each capable of 10/100/1000-Mbit/s Ethernet packet switching (the Prestera 98MX630/620 for MAN/core systems, and the 98EX130/120 for Enterprise systems).
On the network side, the packet processor ties into a physical-layer device such as the company's Alaska family of Gigabit Ethernet transceivers. On the other side of the packet processor is a 15-Gbit/s expansion bus and an interface to the Prestera switch-fabric adapter. The Prestera fabric adapter, in turn, ties the line to a high-performance switch fabric using either a CSIX-compatible parallel bus or a serializer/deserializer (SERDES) serial interface.
Although the line card will contain several other circuits, the Alaska family of Gigabit Ethernet Transceivers, the Prestera packet processor, and the Prestera fabric adapter form the basic architecture of the line cards. Depending on which version of the packet processor chip is selected, each line card can provide either one 10-Gbit channel or 10 1-Gbit channels (Fig. 2). Multiple line cards can then be connected to the switch fabric that will be formed using a fourth chip currently in development at Marvell.
From an architectural viewpoint, all four versions of the Marvell Prestera packet processors are similar. However, the MAN/core versions can perform full wire-speed L2 bridging, L3 routing and L2 to L5 advanced traffic classification, filtering, and prioritization. The 98MX620 and 98MX630 also provide powerful MPLS, NAT, and bandwidth provisioning functions. In addition to a rich feature set, the 98MX620 and 98MX630 take advantage of the scalable memory architecture to support millions of IP routes and flows.
The Prestera 98EX120 and 98EX130 focus on the Enterprise market requirements. They offer full wire-speed L2 bridging, L3 routing, and L2 to L5 ad-vanced traffic classification, filtering, and prioritization. But they don't handle MPLS, and they lack traffic metering and billing abilities. Compared to the Prestera MX devices, the Prestera EX packet processors also support smaller IP and flow tables.
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