At one time, IC design was, if not easy, then at least somewhat simpler. But as the world's semiconductor foundries plunge deeper into the submicron realm, designers face exploding complexity.
Issues such as signal integrity and timing closure are made significantly more difficult by the tightening proximities of interconnects, and by dynamic effects like IR drop and simultaneous switching, all of which are increasingly interdependent at submicron geometries. Also, parasitic extraction has been complicated by a growing need to consider the inductive component. The result is an extremely complex set of parameters that must be analyzed in concert.
Successful design at 0.13 microns (µm) and below de-pends in large part on understanding the physical effects, and on a design methodology that accurately models active devices and interconnects. Not only must models be accurate, but the base assumptions made regarding physical effects must be consistent through a hierarchy of abstraction that incrementally adds physical detail.
Not too long ago, IC designers were able to assume that almost all delays in gate-level simulations occurred in the gates themselves. The interconnects, or wires, between the gates were almost entirely disregarded. Designs were approached as if the architecture required to meet timing, power, and area constraints could be determined by looking only at the gates themselves.
But as design rules fell below 1 µm, that scenario changed rapidly. The crossover point at which interconnect delay caught up with gate delay occurred at 0.25 µm (Fig. 1). At geometries smaller than that, interconnect begins to dominate as the leading source of circuit delay. That's because the aspect ratio of the wires has changed. "They're taller and have more sidewall capacitance," explained Rajit Chandra, PhD and vice president of technology at Magma Design Automation. As a result, the electrical activities in the neighboring wires affect the signal propagation times on any critical wire.
"If you're starting from register transfer level (RTL) to create a circuit that will meet all of your constraints, and trying various combinations of multipliers, adders, and shifters while basing that on a poor interconnect model, it's a waste of time," says Tom Ferry, vice president of marketing for physical synthesis at Synopsys. Why?
The answer is that the fundamental paradigm of assumptions has changed. The statistical wireload models used at larger geometries, which assumed the entire delay was in the gate, are no longer valid. Instead, designers must delve much deeper into the physical realities of the circuits, accounting for many interdependent variables (see "Interconnect Along The Implementation Trail," p. 58).
The nature of the models themselves can be an issue. Now the old paradigm's statistical wireload models, which assume an average capacitance for each load, are outmoded.
"When you didn't have to worry about wires, you could do a logical gate-level optimization, just in terms of fanout and levels of logic, and get pretty good results," says Noel Strader of corporate technical marketing at Avant! Corp. But using a statistical average for loads across an entire library of models will no longer work. Say that for a gate fanout of three, assume an average load of 5 pF, and that as you're performing gate optimization, you're using that 5-pF load in your calculations. Some of those loads may be significantly higher or lower, depending on actual routing. Using these averages could result in a setback in achieving timing closure.
Estimates on where wireload models begin to break down vary somewhat. According to Steve Carlson, director of marketing at Get2Chip, statistical models don't work well for design blocks of more than 20 to 50 kgates. "For the typical design with 1 to 2 million gates and a 200-MHz clock, I would say that's the range in which you start to see problems. And certainly above that, you see problems," he says.
Overcompensating for poor models can produce a range of downstream problems. "When you overestimate or make your timing constraints more stringent than they really need to be on your critical paths, you're going to compensate by sizing up all the drivers," says Magma's Chandra. "Then noncritical nets will seem much weaker in their driving strengths than the critical ones," he explains.
Reprints
