Parallel buses are giving way to high-speed serial/pseudoserial buses, especially in I/Os and system interconnects. Buses like PCI and PCI-X, the universal PC I/O and embedded system buses, will transition to a serial bus, the 3GIO (see the figure).
Developed by Intel, 3GIO will be used in PCs, both servers and desktops, to link fast peripherals to the CPU chip set. PCI and PCI-X will remain to integrate lower-speed peripherals, bridging via 3GIO to the CPU chip set.
This transition involves more than Intel, as the company has turned the 3GIO specification over to the the PCI Special Interest Group (PCI-SIG). The SIG will produce its own specification for 3GIO, renamed Arapahoe. The new specification is expected to be out for review in the second quarter of next year from the Arapahoe Working Group, an industry organization made up of Compaq, Dell, IBM, Intel, and Microsoft.
3GIO is a high-performance, full-duplex serial bus, signaling at 2.5 Gbits/s both ways with 8/10-bit encoding. Each port is made up of differential, self-clocking signal pairs. 3GIO provides a PCI-like interface and operation to the host to minimize software and system changes for the transition to 3GIO.
The serial bus can be deployed in multilink bundles—x1, x2, x4, x8, x12, x16, and x32—for wider-bandwidth connections.
Also, Intel developers went beyond the classical serial point-to-point connections: 3GIO includes a 3GIO switch to provide multiple-link capability. It can also act like a switched multiplexer, aggregating multiple serial line bundles into a single-point interface, such as to the CPU chip set.
The 3GIO serial bus defines a 3-layer protocol: Transaction, Data Link, and Physical layers. It uses a simple packet (Packet Sequence#, Header, Data Payload, CRC). The 3GIO protocol implements a credit-based flow control. Packets are transmitted only when the receiving node has buffer space.
All 3GIO transactions are issued as split transactions, separating operation requests from the actual operations. The transaction layer supports the three PCI address spaces and a Message Space. It also implements PCI2.2's message-based interrupts (Message Signaled Interrupts, or MSI).
The 3GIO serial bus supports hot- attach/detach, power-management, quality-of-service (QoS), and reliability, availability, and scalability (RAS) capabilities. Its switch topology handles up to 256 components. 3GIO, or Arapahoe, is expected to start deploying in the second half of 2003.
For more details, contact Intel at (408) 765-8080 or www.intel.com/technical/3GIO, or the PCI-SIG on the Web at www.pcisig.com.
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