The idea of field upgrades of reprogramming FPGAs is a key attraction to designers. Unfortunately, field-upgrade meth-odology has been pretty much left to the engineer. Xilinx's Pave 1.0 Framework changes that. It enables designers to reprogram their Xilinx Spartan II and Virtex FPGAs via a host framework that works with the target system real-time operating system (RTOS) over the Internet.
Using Pave, developers can make remote customer-premise equipment design changes for integrated FPGAs—and they can do this in a structured, down-the-line methodology. Pave is part of Xilinx's Internet Reconfigurable Logic Technology (IRL). The host connects to a target processor running the VxWorks RTOS. This target processor, in turn, can upgrade any registered FPGA on a board accessible across the target system bus.
PAVE consists of a host-based system integration framework (SIF) and an application programming interface (API) for C++ programs. Engineers build the reconfiguration files using C++ programs. The files are shipped to the target processor, which uses the API to reprogram the FPGAs via a configuration register. The reconfiguration is performed using Xilinx's SelectMAP or IEEE JTAG programming methodologies. The SIF supports a target board directory, defining each target board and its reconfigurable components.
The PAVE SIF framework and IRL Design Guidelines Cookbook are available for free from Xilinx. The target needs a 32-bit configuration register (between the CPU and the FPGA) and a VxWorks-hosted CPU board. The development host needs Windows NT 4.0/Win2000 with Wind River's Tornado integrated development environment.
Xilinx, 2100 Logic Dr., San Jose, CA 95124-3400; (800) 255-7778; www.xilinx.com.
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