[Technology Report]
Up SoC Performance With Configurable/Extensible Microprocessor Cores
Use configurable and extensible soft CPU cores to deliver high-efficiency SoC and ASIC designs.
Every engineer wants a microprocessor to fit an application like a glove. But nobody wants to design a micro for a specific application. Too expensive. Too much work. But today, engineers can get a tailored microprocessor without paying the design price. ASIC and system-on-a-chip (SoC) designers can configure or extend an existing CPU core to meet their application requirements.
Instead of a fixed RISC microprocessor, engineers can tailor a scalable core with add-on features. Some cores also are extensible. Developers can add new instructions, new functions, and new interfaces to them.
Adding a few key CPU resources or instructions can deliver huge dividends in performance, cost, and throughput efficiency, especially for embedded or telecom applications. One method for designers is to monitor their initial application code, find the expensive processing and inner loops, and then increase efficiency by adding special features, instructions, or coprocessor blocks.
These features can include complex math-processing blocks and complex multicycle instructions. These extensions all play under the umbrella of a standard microprocessor core complete with a software development chain that includes compiler, assembler, and debugger, as well as a full set of standard HDL-based, EDA tool chains.
Moreover, these configurable/extensible cores may play a major role in ASIC multiprocessing, especially for data-flow applications like telecom and video. These applications typically consist of "n" data streams that are processed in multiple process stages.
For example, in telecom, multiple lines are pumping in packets, which need stage-by-stage processing—identification, checking, and packet assembly/disassembly. This processing can be implemented as an array of processors.
On the X or horizontal axis, a line enters the array and passes through multiple processor stages. For multiple lines, these stages form processor layers in the Y dimension. Each Y layer consists of processors tailored to that stage's specific task. The resultant array provides staged processing for multiple lines, with each stage delivering high-efficiency processing.
Today's configurable/extensible cores include ARC's Tangent A4 and A5, and Tensilica's Xtensa architectures.
Not Rocket Science The first thing to understand is that configuring or extending a microprocessor core isn't rocket science. It's much easier than one would think. For one thing, the cores aren't super-sophisticated RISCs with long, complex pipelines and multi-issue superscalar execution. Rather, like ARC's Tangent and Tensilica's Xtensa, these cores are basic RISCs with relatively simple architectures and pipelines. They tend to:
Have short pipelines of four or five stages long;
Be simple scalar machines of one instruction issue per clock;
Be simple Harvard or Von Neuman implementations;
Have a core set of basic instructions;
Provide a larger set of additional instructions to add;
Have an expandable core register set;
Provide lots of bit manipulation and branch instructions;
Support I, D caches and memory options.
Today, most designers understand the basic RISC design methods and architectures. These soft cores fit right in. Most engineers will feel right at home adding defined features and instructions. Both ARC and Tensilica provide interactive architecture design environments that make it easy to add predefined features, like general registers or instructions. That can be done via pull-down menus.
Adding a simple instruction doesn't require a computer architect's expertise. For starters, the architectures are simple four- or five-stage pipelined RISCs. Most new instructions, which generally use existing datapath structures, can execute in a single "execute" cycle. Therefore, it's generally a matter of defining operations within a cycle.
The key to these configurable/extensible cores lies in two factors. First, because they're soft cores, all changes and additions can be compiled in to create a new expanded synthesizable processor core. Second, changes to the core architecture are accompanied by equivalent support in the software and hardware design tool chains. New registers and instructions are reflected in the core's assembler, compiler, and debugger. Tensilica, for instance, generates intrinsic functions to represent the additional instructions or instruction blocks added. Developers can use the "instruction" or "block" in early code to test it without waiting for the final silicon.
Both ARC and Xtensa target embedded applications. They both implement shorter 16-bit instructions for code compactness (smaller than ARC's 32-bit and Xtensa's 24-bit ISAs). They also implement built-in automatic loop control with loop instructions that set up a loop count and an inner loop boundary (start, end).
For instruction configurability and extensibility, both ISAs are structured to support instruction expansion. Each ISA implements multiple layers of instructions using multiple op-code fields (op code, sub-op code, etc.) in each instruction word. ARC implements one sub-op code field. Xtensa uses two.
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