There's change in the wind for designers as IC geometries shrink and transistor counts rise. Design methodologies must move with the physical silicon. Clearly, hardware-description language-based methodologies increasingly are a hindrance to simulation and verification. It's time for designers, as they did a decade ago, to consider moving up a level of abstraction.
In the world of design languages, change is driven by rising design complexity. For example, by the late 1980s, ASIC designers had begun shifting from schematic-capture-based design methodologies to the emerging hardware-description languages (HDLs). This move to the higher level of abstraction, represented by the register-transfer level (RTL), helped designers regain control over the rapidly escalating complexity.
The early 1990s are remembered for the so-called "language wars," as Verilog, VHDL, and other HDLs competed for market share. The invention of synthesis technology by Synopsys propelled Verilog to prominence in 1988. It enabled the synthesis of Verilog hardware descriptions directly into gates. In 1991, Cadence made Verilog an open standard; it became an IEEE standard in 1995. Verilog became the veritable 800-lb gorilla in RTL design and has been ever since.
Today, a similar scenario is developing. A new "language war" is brewing in which a number of system-level design languages (SLDLs) are touted as the means to not only speed up simulation for these large ASIC/SoC designs, but also to address hardware/software partitioning and coverification in one fell swoop. Standards organizations such as Accellera are working to solidify these languages, while industry consortia like the Open SystemC Initiative work to rally support.
While most, if not all, large system OEMs already incorporate some form of system-level design exploration into their flow, this isn't the case with most smaller companies. There are good reasons to consider using high-level languages before starting the long, hard slog through simulation at the RTL. But know that it's still early in the game for SLDLs. Track records are spotty in terms of going all the way to implementation from a high-level design description. Tool flows are still coming together. Indications show that it can be done, but not painlessly.
Let's define exactly what's meant by "system-level design." To most EDA tool vendors, it means the exploration of SoC/ASIC architectural tradeoffs at a level ahead of partitioning the system's functionality into hardware and software. System-level design is certainly at a level above RTL. "It's pretty clear that if you're talking system-level design, you're talking more than just behavioral synthesis of hardware blocks," explains Stan Krolikoski, vice president of business operations for Cadence's Systems and Functional Verification Group.
"You're talking about the relationship of hardware and software, the relationship of hardware blocks to other blocks within your system, and about parts of your system that sometimes are ignored, namely the communication links, like buses, and what their effects are on the whole," he explains.
Others would maintain that system-level design implies a way to describe a system algorithmically. It should also include a mechanism for checking assertions about the design.
Foremost among the reasons for altering a design methodology to include a system-level layer is the simulation and verification issue. With SoCs and ASICs ballooning into the multimillion-gate range, simulation of a smidgen of runtime can take weeks. A design description at a higher level of abstraction can remove much, if not all, of the implementation details that bog simulators down while retaining the pure functional information. The result is much faster simulation and more time for what-ifs, tweaks, and other stabs at an optimal architecture.
Another major benefit is in hardware/software codesign and coverification. An increasingly large part of any system's functionality is implemented in software. Higher levels of abstraction can make it easier to observe the behavior of a system in total, as the system architect begins pondering the difficult issues related to partitioning.
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