[Product Innovation]
10-Gbit/s Transceiver IC Delivers Jitter-Free Data
Secret ingredient in new IC is the key to meeting and beating all jitter specifications.
As Sonet, Ethernet, and other optical transmission standards push for higher data rates, jitter becomes one of the most critical design issues. Jitter has always been a nuisance. But at OC-48 and OC-192 Sonet speeds, and at 1- and 10-Gbit Ethernet speeds, it be-comes the limiting factor in many designs. Now, Silicon Laboratories of Austin, Texas, has developed an IC that greatly mitigates the jitter problem. It offers superior jitter performance of 5 mUI rms on the transmit clock line at an OC-192 rate of 10 Gbits/s (see "Jitter And Its Measurement," p. 50). The small but highly integrated 0.15-µm CMOS Si5600 SiPHY OC-192/STM-64 Sonet/SDH transceiver also features low power consumption.
Designed for serial communications at data rates from 9.9 to 10.7 Gbits/s, the device can be used in OC-192 applications that call for 15/14 forward error correction (FEC). It contains a 16:1 and 1:16 serializer/deserializer (SERDES), a clock and data recovery (CDR) circuit, a clock multiplier unit (CMU), and a limiting amplifier (Fig. 1). The device operates from 1.8 V over the −40°C to 85°C temperature range and dissipates an average of 1.2 W.
The chip is designed for use in almost any Sonet/SDH equipment, including routers, add/drop multiplexers, digital cross connects, optical transponder modules, and Sonet/SDH test equipment. It can also be employed in 10-Gbit Ethernet products.
The receiver part of the Si5600 gets its serial input from the optical diode and its transimpedance amplifier. It incorporates a sensitive limiting amplifier with ample gain, eliminating the need for other external amplifiers. The limiting amplifier fully saturates with as little as a 20-mV p-p differential input. Input signals exceeding 1 V p-p produce no performance degradation.
Moreover, the limiting amplifier incorporates a digital calibration algorithm that helps to cancel out amplifier offsets. It uses statistical averaging to remove noise that may degrade traditional calibration techniques. The amplifier also features loss-of-signal (—LOS) detection circuitry. The —LOS output is driven low when the input to the limiting amplifier goes below a desired preset value of about 10- to 50-mV p-p differential. This level is set by applying an external reference voltage of between 0.2 and 0.8 V to the LOSLVL pin. Built-in hysteresis of around 3 dB prevents unnecessary switching on the —LOS line. Tying the LOSLVL line high disables the —LOS line, forcing it high.
The CDR circuit rebuilds the clock from the serial NRZ input data. The recovered clock can then regenerate the data by sampling the limiting amplifier's output at the center of the NRZ bit time. The CDR also has a phase-adjustment feature that permits selecting the sampling instant used for data recovery. This sampling point can be moved over a ±45° range relative to the center of the incoming NRZ data period. This is useful in applications where the transmission medium introduces severe distortion, making data recovery difficult. Phase adjustment is made by applying a 0.2- to 0.8-V voltage to the PHASEADJ pin.
Next, the recovered data is converted into a 16-bit parallel output word by a 1:16 demultiplexer. The outputs are low-voltage differential signaling (LVDS), compliant to the OIF SFI-4 low-speed interface standard. The receive clock (RXCLK1 or RXCLK2) that multiplies the output data is derived by dividing the recovered line clock by 16.
Interestingly, the order of the receiver parallel outputs may be reversed. If the RXMSBSEL control line is tied low, the first bit received is placed on the RXDOUT0 output line, with the re-maining bits on the successively higher RXDOUT pins. But if the RXMSBSEL line is made high, the first bit received is sent to the RXDOUT15 output pin, with the following bits in reverse order.
A FIFO, a parallel-to-serial shift register, and the CMU make up the transmitter. The FIFO is eight 16-bit registers deep and provides a way to compensate for any phase delay or wander in the clock speeds of TXCLK16IN and TXCLK16OUT. The 16-bit LVDS input data is latched into the FIFO, then ultimately transferred to the shift register. From there it's transmitted serially at line speed under the control of the TXCLKOUT signal.
The shift register is set up to transmit MSB or LSB first. If TXMSBSEL is set low, then TXDIN0 transmits first. When TXMSBSEL is set high, TXDIN15 transmits first. This feature, like that in the receiver, can help in pc-board layout by simplifying bus routing in multichip, multiside board layouts.
The CMU takes the input reference clock and multiplies it by a factor of 16 or 64 to the final serial data rate. For a clock rate of 10.66 Gbits/s, the necessary rate for Sonet with FEC, the reference clock would be either 167 or 666 MHz. The TXCLKOUT signal operates the shift register.
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