[Design Application]
Built-In Self-Test Streamlines Testing Of Mixed-Signal SoCs
Histogram-based BIST techniques harness on-chip resources to reduce test times and cost while keeping pace with increased circuit complexity.
As the integration between digital and analog circuitry in-creases in system-on-a-chip (SoC) designs, the challenge of testing these mixed-signal functions be-comes increasingly complex in terms of test development time, automatic-test-equipment (ATE) complexity and cost, and production test times. There are some built-in self-test (BIST) methodologies available today that enable the analog portions of an SoC design to effectively test themselves. They also can report results in digital format, minimizing the impact of this increased integration.
This reduced impact is particularly true for analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and voltage-controlled oscillators (VCOs). Employing a technique called histogram-based analog BIST (HABIST), the results of analog circuit tests can be converted to digital test results. The resulting digital data can then be analyzed for such parameters as integral and differential nonlinearity, gain and offset errors, effective least-significant bit (LSB), and clipping and modulation distortion.
During an HABIST implementation, essential information about the signal under test is converted to a histogram, from which characteristics can be studied to gain valuable information about circuit performance. The sample-and-hold circuit and the ADC perform the conversion from the analog domain to the digital domain (Fig. 1). Once the data from the ADC is fed to the histogram generator, the results can be downloaded and read by a digital ATE system.
The technique uses undersampling of the analog signal(s) under test to quantify how long the signal remains at each amplitude level, placing the values in various bins in a histogram (Fig. 2). The histogram characterizes the waveform of the signal under test, capturing its essential elements.
Using software simulation tools, an ideal histogram for each signal under test can be created, as can histograms for signals due to certain defects, like stuck bits and various types of nonlinearity and distortion. These signatures for various types of faulty circuit behavior can be stored for use in determining the pass/fail status of analog circuits under test during production testing.
Should the signal under test vary from the expected signal, the histogram normally undergoes significant changes (Fig. 3). The clipped sinewave shown doesn't spend nearly as much time at the high and low boundaries. Therefore, the resulting histogram has fewer entries in the outside bins and many more entries in the bins adjacent to them. Subtracting the acquired histogram from the ideal histogram creates a difference histogram that can be analyzed to determine which defects are present in the circuit under test.
In addition, the histogram-based method can be deployed to test the ADC that's part of the circuit itself when a proper stimulus signal, usually a ramp, is applied to its input. The ramp signal can be supplied either by an external signal generator or by a DAC that might already be present in the design (Fig. 4). Multiplexers at the DAC inputs and output allow it to be employed not only for on-chip functional purposes, but also as the stimulus generator for ADC testing.
The results from the histogram-based BIST circuitry can be accessed by a digital-only ATE, offering significant savings in cost as well as complexity. The IEEE-1149.1 (standard protocol from JTAG for Joint Test Action Group) testability bus interface, normally included in the design to provide access to the on-chip boundary-scan circuitry, can be used to access the HABIST results. (Boundary-scan circuitry enables interconnect testing during board assembly.) These are placed in a user-defined test data register and accessed by the standard 1149.1 protocol.
The same histogram-based technology applies to DACs. It can solve the many problems that designers encounter when the DAC is embedded in a complex SoC design.
Traditionally, DACs have been tested by successively applying all of the digital codes to the DAC input signals to cause the analog output of the DAC to swing over its entire range. Analog instruments are then typically used to measure the DAC output voltage in response to each input code. These discrete measurements are examined to determine the gain and offset parameters of the DAC under test and to calculate its integral and differential nonlinearity.
Some common problems are associated with these traditional methods. A mandatory test time is required to fully exercise all of the DAC codes. Other problems include analog instrument-measurement errors, settling times, and the controllability of the DAC digital inputs. All of these issues can be addressed with a variation on the basic HABIST methodology.
Let's refer to the previous example configuration (Fig. 4). After the ADC is tested through the HABIST implementation, the tested ADC can be used as the on-chip measurement instrument for any embedded DACs to be tested. A multiplexer at the DAC output routes the signal under test to the integrator and comparator circuitry. Next, the BIST circuitry simply treats the DAC output as another analog signal to be evaluated, reading the data digitally and analyzing it by histogram methods.
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