[Technology Report]
DRAM Derby Heads For The Stretch
The DRAM market is fragmenting as emerging architectures—DDR SDRAM, FCRAM, DRDRAM, and RLDRAM—compete for next-generation sockets.
DRAM means cheap, standardized memory. We need lots of DRAM to feed our faster processors and ever-expanding network infrastructure and devices. Unfortunately, cheap memory usually means a standard DRAM form accepted by the industry. And that's not going to be. DRAMs are fragmenting into competing architectures—RDRAM, DDR SDRAM, FCRAM, and RLDRAM (see the table).
Moreover, the DRAM application market is fragmenting as well. The DRAM world, with its single-minded standard that we've known and built on, is ending. There will no longer be a single dominant PC-based DRAM architecture. Instead, designers can choose from multiple DRAM architectures. But with that flexibility will come the end of the era of really cheap DRAM. A fragmented market will make it difficult for DRAM vendors to ratchet up production to reach commodity-level pricing. DRAMs now include:
SDRAM—Synchronous DRAM. Current mainstream SDRAMs clock at 133 MHz, with some at 167 MHz.
DDR SDRAM—Double Data Rate SDRAM, which clocks data on both clock edges.
DRDRAM—Direct Rambus DRAM, which uses a high-speed, narrow memory bus and packetized commands, with controllers on both the memory and host sides.
FCRAM—Fast Cycle SDRAM, which speeds up the access cycle and cuts power.
RLDRAM—Reduced Latency SDRAM, which reduces access latency and power.
Applications In its glory days, PC-based DRAM had over 70% of the DRAM market. Today, it's a bit above 50% and falling as other markets take larger shares. For example, the share of telecom/datacom servers is growing and will perhaps equal PCs in four or five years. Other applications, like Internet devices, portables, PDAs, and multi-use PCS phones, are building in DRAMs, expanding their market share. Games too have proved a good DRAM base: each Sony Playstation2 has 32 Mbytes of RDRAM.
On the PC front, the battle is between DDR SDRAM and RDRAM. Both deliver high-bandwidth performance: RDRAM over a narrow, high-speed channel, and DDR SDRAM over a wide memory bus. It's too early to project a winner, although RDRAM has an early edge. Intel's 850 chip set for the emerging Pentium 4 has a two-channel RDRAM controller.
However, Intel competitor AMD can't be discounted. AMD has made benchmark hay, beating out the Pentium 4 with its Athalon CPU and 760 chip set teamed with DDR SDRAM. Complicating matters, Intel has moderated its commitment to RDRAM with a new PIV chip set for DDR SDRAM and SDRAM, due out late this year or early next. Additionally, DDR chip sets are emerging from other vendors. In graphics memories, though, DDR seems to be winning hands down.
Server vendors are building on PC133 SDRAM and the emerging PC167 for their wide-access buses. But they're also starting a slow shift to DDR SDRAM, which supports wide-bus implementations. Telecom applications are already accommodating DDR for wide-bus implementations. Yet newer, faster-access FCRAM and RLDRAM also seem to be making inroads into new designs. Both work from the DDR SDRAM interface, so they don't present any major redesign problems.
For the low end of the DRAM market, such as portables, lower power has been a must. New DRAMs, low-power SDRAMs, FCRAMs, and RLDRAMs are on the way to fill that need.
DDR SDRAM DDR SDRAM is evolutionary, an extension of the current DRAM standards. Simply put, DDR is SDRAM clocked twice, delivering twice the memory bandwidth. Currently, DDR SDRAM supports 100- and 133-MHz versions. Coming is a 167-MHz version. All deliver burst data at twice the clock rate, or from 200 to 333 Mbits/s per pin.
DDR-II, the next generation, is already under development. It will move DDR clock rates to 200 to 400 MHz, delivering 400 to 800 Mbits/s per pin. For a standard 64-bit bus, DDR delivers 1.6- to 2.7-Gbyte/s burst rates. DDR-II will pump this up to 3.2 to 6.4 Gbytes/s.
DDR SDRAM clocks in data from the memory bus twice in a single clock, at twice the clock rate. Yet internally, in its core memory array, it accesses at the input clock rate an array that's twice as wide. It brings in or writes two words per clock. But those operations are done in a single, double-word Read or Write.
It supports burst operations with bursts that are two, four, or eight cycles long. The design includes standard Auto Refresh and Self Refresh modes. Reads and Writes are burst-oriented, starting at an addressed location and counting up in address for a programmed number of cycles. Auto precharge kicks in at the end of a burst access. It hides row precharge and its activation time.
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