Core embedded applications increasingly demand more processing power, higher math capability, and faster processors. Driving these needs is a shift to more processing power to replace expensive sensors, to achieve closer motor control, and to support Internet, speech, and audio needs. One solution is faster, more powerful 16-bit controllers that also deliver DSP math power—and that's what the new dsPIC, the 16-bit MCU/DSP from Microchip Technology, is all about.
The dsPIC integrates a 16-bit microcontroller with a 16-bit DSP (Fig. 1) But instead of creating a totally new architecture, Microchip transformed the popular 8-bit PIC architecture's ISA into a 16-bit MCU/DSP, resulting in the dsPIC. It's upward-compatible to the PIC18xxxx. You can compile and assemble PIC18xxxx code and run it on the dsPIC. Engineers familiar with PICscan can easily step up to the new 16-bitter (Fig. 2). The dsPIC's designers did more than extend the 8-bit PIC ISA. They also built a new architecture with improved performance, programmability, C compilability, and RTOS execution.
Running at 30 MHz, the dsPIC delivers a peak 30 MIPS (25 MIPS typical). Designed for control, it incorporates advanced bit manipulation, fully interruptible operation, and prioritized interrupts. On the DSP side, it delivers a full 16-bit, single-cycle MAC DSP with dual 40-bit accumulators. This is a tuned architecture that minimizes hardware overhead, but provides the key resources. For example, it supports a full 16- by 6-bit register file, the W registers.
A DSP And µC One way to add processing power is by implementing a DSP. In fact, many applications, such as cellular phones and disk controllers, previously included both a microcontroller (µC) and a DSP. (Now the trend is to a single chip.) Unfortunately, classic µCs and DSPs differ. The former control well, but lack math horsepower; the latter do math well, but lack many real-time control features. µCs routinely handle multiple interrupts with fairly low latencies. Conversely, DSPs tend to lock out interrupts when processing inner loops, or they can only perform limited interrupt processing there.
A DSP's main architectural difference is that it supports inner-loop MAC-type processing, typically used to build a series. This inner loop consists of some control and many MAC (or other accumulator function) instructions. Each MAC operation—a multiply (a constant times a variable)—is a single-cycle operation (pipelined). An automatic fetch of the X and Y variables and an automatic loop control for single-cycle MAC execution support it. DSPs, which accomplish many operations in a single cycle, are the last of the CISC machines.
The dsPIC supports X and Y memory accessing, a set of MAC-type operations, and zero-overhead loop control. It functions as a DSP and an MCU, with both sharing the instruction load and decode logic. The MCU has its own adder and register set, but the DSP unit also operates with the MCU general register set, the W registers that also serve as the MCU's register set.
Generally, while either DSP or MCU instructions execute, the other lies idle. In the Euclidean Distance instructions, however, both the DSP and MAC arithmetic logic units (ALUs) are used. During DSP operations, results are stored in DSP result registers but can be explicitly written to W registers.
The DSP engine executes a MAC-type instruction in one cycle by prefetching the X and Y data values in the previous cycle and dropping them into the W registers for the next MAC cycle. In a sense, the dsPIC is pipelined.
The system supports 32 kwords of data memory, partitioned into X and Y data spaces. Y, a subset of X, is only used for DSP operations, while the X space is used for both MCU and DSP operations. The X and Y address generators supply X and Y data-access addresses for single-cycle MAC operations. In addition, the hardware implements DO (loop) and Repeat instructions to support inner-loop and multiple-instruction execution. These can run single-cycle MAC-class instructions using hardware register counters to monitor loop or instruction counts for zero-overhead looping.
MCUs normally shine at bit-manipulation, which is necessary for control and fast RTOS operation, whereas bit-manipulation instructions are a fairly new addition to most DSPs. The dsPIC has an outstanding set of bit-manipulation operations for both MCU operations and DSP operand scaling. For starters, the dsPIC extends the bit-manipulation features of the earlier PIC18xxxx.
But the dsPIC goes much farther in bit manipulation. It implements a set of Bit Find Operations that enable the software to find the first active bit in a data word. These powerful operations eliminate the need to search a word's bits, bit by bit, to find the first marker bit. They support scaling of the DSP operands and can find a scaled value to help set its exponent. They also support normalization of the accumulator values for efficient 16-bit word storage and help to speed up RTOS processing that involves bit checking, like interrupt polling, task switching, and I/O bit processing.
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