[Technology Report]
Programmable Logic Now Bestows Configurability Upon All Kinds Of Chips
No longer a standalone technology, programmable logic is penetrating ASICs, mCs, SoCs, ASSPs, and eventually ICs. Look for programmable ASSPs to be a mainstream trend.
Programmable logic is going mainstream. Programmability, or rather configurability, will no longer be confined to glue logic, datapath chips, or special processing functions. Instead, programmable logic will become the glue to extend configurable logic across the full range of digital design. System and logic design will increasingly shift to programmable ASSPs—application-specific standard parts that are configurable via programmable logic.
Programmability has always been an attractive goal. Previous constraints, like limited silicon resources, slow programmable logic, and ineffective tools, confined the reach of programmable-logic design. Today, those limitations are rapidly falling off, opening up programmable logic as a key design technology in several areas. These include programmable IP for ASICs, FPGA-enabled ASSPs, configurable microcontrollers (µCs), and programmable system-on-a-chip (SoC) platforms.
Programmable logic is slower and much larger than comparable standard-cell functions. Yet, it delivers reconfigurability—i.e., the ability to reconfigure the logic design on a finished chip. Reconfigurability is gaining importance to system and logic designers, especially standard-cell ASIC designers. With on-chip reconfigurability, they can build multiple versions of the same basic design, each targeting a different aspect of the market.
The ability to leave part of the design open to later changes is critical for ASICs that rely on rapidly evolving communications, bus, and interconnection standards. Spare logic lets designers upgrade the standing logic to match newer requirements.
Designers need to be able to fix or work around logic errors found downstream in the product cycle. With FPGA-based control, they can upgrade algorithms without doing a new mask set.
The first capability supports treating ASIC designs as programmable ASSPs that can be tailored for specific requirements. So, a single mask set can serve to drive multiple ASSP chips. This will become an increasingly important feature as the price of mask sets rises with higher silicon densities. A mask set for 0.18-µm CMOS runs around $300,000 to $350,000, one for 0.13-µ>m CMOS costs about $500,000, and a mask set for 0.1-µm CMOS could be $750,000 or more. Programmed configurability lets engineers define multiple ASSPs from a single mask set for a tre-mendous savings.
Moreover, rising silicon size and pinouts may make sufficient "white space" available in ASICs to accommodate programmable-logic IP without compromising chip design. For pin-limited ASICs, silicon real estate often is virtually free for additional IP, except for increased power and test budgets. This enables the addition of design luxuries, such as programmable logic, to large-pinout ASICs.
Two vendors, Adaptive Silicon and Actel, both field RAM-based FPGA IP for ASICs. Adaptive Silicon has developed a programmable-logic system for IP deployment with a wrapper and built-in interface. Supporting up to 25,000 ASIC system gates at clock rates up to 100 MHz, Adaptive's MultiScale Array (MSA) was designed for both control and datapath usage. It handles wide datapaths and adders (Fig. 1).
The MSA 2500 builds around a 4-bit logic slice. This slice can be configured as a 4-bit ALU with control logic and fast carry-look-ahead, or as a set of four three-input lookup tables (LUTs). A block of four slices forms a quad block, and a 4-by-4 set of quad blocks makes a hex block, the smallest deployable IP block. The FPGA has local and global routing resources.
Another FPGA IP offering is Actel's VeriCore. It's based on RAM, and it supports up to 40k programmable system gates running at up to 100-MHz rates. The basic logic cell is the logic unit, which consists of two three-input LUTs feeding into a multiplexer and a flip-flop. The logic units are organized into sets of four, with one functional group in total. A PEG consists of 64 functional groups, and it holds about 2.5k system gates. The VeriCore architecture centers on a block of PEGs that are supplemented by optional hard RAM and I/O blocks (Fig. 2). The architecture can have up to eight optional RAM blocks, with up to 73,728 RAM bits.
FPGA-based ASSPs need not be restricted to ASICs. Some vendors are combining existing programmable-logic technologies with hard IP to create their own programmable ASSPs. These include Actel, Agere (formerly Lucent Microelectronics), Cypress, and QuickLogic.
QuickLogic was one of the first programmable logic vendors to recognize the need for programmable ASSPs, especially those that integrate hard standard-cell IP with programmable logic and on-chip RAM. QuickLogic's ASSPs include QuickDSP (for DSP processing), Quick SD (serial input with a serializer/deserializer or SerDes), QuickPCI, and QuickRAM.
Such FPGAs use QuickLogic's programmable antifuse, ViaLink, and have a multiplexer-based basic logic cell with holding register bits. The Quick FPGAs provide up to 662 kgates and 83 kbits of RAM. The QuickDSP has a layered architecture, consisting of a dual-port SRAM layer, a layer of Embedded Computation Units (ECUs), an FPGA logic layer, and a bottom SRAM layer. The ECUs integrate MPY, ADD, and accumulate functions.
Agere fields what it calls its Field-Programmable System Chips (FPSCs), a combination of special hard-application IP with the company's ORCA programmable logic. Because Agere is both an ASIC house and an FPGA vendor, this combination works well. Its latest FPSC, the ORT8850, implements an eight-channel by 850-Mbit/s backplane transceiver. This chip delivers Sonet connectivity and is back-ended by an FPGA array for application logic and interfaces. The FPGA supports between 260,000 and 970,000 system gates, with internal clock rates of up to 250 MHz.
From Cypress, the Programmable System Interconnect (PSI) is another programmable ASSP. Designed to support high-speed serial interconnections, such as serial backplanes, the PSI chips integrate up to eight serial channels with a SerDes, a set of datapath registers, and a CPLD. The chip handles 2.5-Gbit/s serial data rates. The back-end CPD supplies up to 200k usable gates and up to 480 kbits of integrated memory (with up to 96 kbits of dual-port or FIFO RAM).
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