[Design Application]
Automated Top-Down Design Rapidly Becoming Essential For Mixed-Signal Circuitry
Bottom-up design verification is yet another critical step in the process.
Nowadays, the methodologies of top-down design and bottom-up verification are well accepted standards in the world of digital design. But this wasn't always the case. Prior to the availability of hardware description languages (HDLs), when designs weren't as complex, there was no pressing need for top-down design techniques. Back then, it was actually possible to go to the detailed transistor design immediately after the release of the system specification.
Today, the top-down technique enables a methodical and systematic approach to complex designs. The methodology allows system-level design flaws to be exposed much earlier in the process, when they're much easier and less expensive to correct.
The same issues that forced digital design into top-down techniques are now pushing analog design in the same direction. In addition to becoming far more complex, today's analog designs frequently contain substantial mixed-signal circuitry, involving increased two-way interaction between the analog and digital portions. System-on-a-chip (SoC) devices feature increasingly more analog components like analog-to-digital converters (ADCs), digital-to-analog converters (DACs), phase-locked loops (PLLs), and adaptive filters—all of which are driving the demand for improved design methodologies.
Typically, analog and digital subsystems are created in isolation and never meet until IC layout. Furthermore, they're not tested together until the silicon returns from fabrication. Obviously, at this point, it becomes ex-tremely expensive to find an inverted bus signal or a faulty interaction between the analog and digital portions. An infinitely superior solution is to simulate the entire system before going to IC layout by using bottom-up verification techniques.
The primary problem hindering the change to analog top-down design and bottom-up verification has been the lack of tool support for the design process between system-level specification and transistor-level implementation, as well as between transistor implementation and chip fabrication. These missing tools are commonly referred to as "The Gap."
The overview of automated design for both digital and mixed-signal branches is depicted in Figure 1. Each branch progresses in incremental steps from specification through transistor implementation to fabrication. Because it's more fully developed, the digital branch flows smoothly from start to finish, with adequate tools in place to support each phase of development. In contrast, the mixed-signal branch is subject to a number of missing tools, as highlighted by the Gap.
Fortunately, this gap is beginning to fill with tools from a number of different vendors. Within only the last year or so, for instance, the industry has introduced behavioral models, standard analog modeling languages, and mixed-signal verification tools.
Key tools already helping to fill the Gap are libraries of behavioral models. These libraries are collections of models that represent the behavior of a device rather than mimicking its actual implementation. The models are implemented at several different levels of abstraction, ranging from, say, a simple ideal op amp to a complex multipole/zero op amp. Plus, each model has dozens of parameters to enable customization for any need. In this way, a library of only 200 parts can be used to model hundreds of thousands of functions. One example of a library of behavioral models is CommLib, produced by Mentor Graphics.
These models also provide a huge benefit in Monte Carlo and Corner Case analysis, two common analog test standards. For instance, in the bad old days, designers had to create 10 different macro-models to perform a 10-point sweep analysis. Performing Monte Carlo analysis with macro-models was virtually impossible. But luckily, behavioral models eliminate these difficulties.
Suppose a model exactly describing a block of a proprietary design isn't available. Analog HDLs enter the picture here to provide the solution. A design team can create its own models, or write custom code, around an existing model to add the necessary additional features. Designers also can purchase the source code for the library model and use it as a basis for a custom library.
Which HDL should be chosen? In these times of partnerships, joint ventures, and purchased intellectual property (IP), it's very difficult to remain isolated to one HDL. So, it's very important that the design simulator accepts all standard HDLs interchangeably—that is, Verilog, Verilog-A/MS, VHDL, VHDL-AMS, Spice, and C-level models, such as Mentor Graphics' ADVance-MS simulator.
Analog HDLs and behavioral libraries enable system designers to quickly write a block-level system model that can easily be simulated to optimize chip performance early in the design cycle. Because it's written in a standard HDL, this system design can be employed as a live specification to pass down to the transistor-level designer or out to a design subcontractor in a language that they and their tools will understand. The standard HDL system design supplies a ready-made test bench, too.
Once in the hands of the transistor-level designers, each block will be logically decomposed, in increasing levels of detail, until the final transistor design is reached. At all points, the analog simulations should run adequately with any partition at any level. This will ensure that each partition is accurately moving down toward the implementation level. Such a methodical approach can shave weeks or months off of the design cycle, helping companies meet their time-to-market deadlines.
To gain a thorough understanding of transistor-level behavior, the detailed design engineer will closely examine any differences between transistor-level design and its upper-level behavioral model. This is the ideal time to "calibrate" the model to the transistor design. If the upper-level model is a CommLib library part, the designer can use the built-in test bench to automatically stimulate and characterize the transistor-level design. If the upper-level model is a custom model, the designer can build a test bench and/or use an optimization tool, such as Mentor Graphics' OPSIM, to match the model to the transistor-level behavior.
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