[Technology Report]
Super-Smart Power Technology Scales Down To Nanometer Design Rules
As suppliers adopt 0.35-μm and finer CMOS features, they seek system-level integration with on-chip power MOSFETs.
With the thrust toward system-level integration, smart power devices continue to make progress on all fronts. This advancement has enabled makers of smart power ICs to implement on-chip microprocessors/microcontrollers and digital signal processors (DSPs), along with logic, memory, control/protection, and high-voltage high-power switching circuits. Over more than two decades of evolution, both low-voltage and high-voltage circuits have learned to live side-by-side in harmony, as on-chip integration levels and power capabilities continue to evolve. Smart power devices have been transformed into what some have labeled "super-smart" power ICs, heralding an era of programmability and software-controlled smart power solutions.
Concurrently, developers are exploring integration techniques to include functions that earlier were impractical. For instance, researchers have embarked on projects to implement silicon-controlled rectifiers (SCRs) instead of conventional power MOSFETs or isolated-gate bipolar transistors (IGBTs) on a smart power chip. For that, they're developing isolation technologies that can allow high-voltage power SCRs to function peacefully on the same die that houses low-voltage control and logic circuitry. Likewise, others seek methods to include sensors and microactuators within the realm of smart power technology. Upon integrating these sensors on a single silicon die, developers are investigating methods to implement microelectromechanical systems (MEMS) within the reach of a monolithic smart power process that can realize a true system-on-a-chip (SoC) solution.
Other Avenues Also Developers have also taken different routes, such as scaling down to deep-submicron CMOS for very high integration densities. Experiments with substrates like silicon carbide (SiC) have shown that submicron CMOS circuits can be built on SiC substrates which are able to accommodate large power structures. Using SiC substrates allows low-voltage control, diagnostic, and protection functions to coexist with high-power devices on the same die.
Speaking of deep-submicron processes, key super-smart power IC suppliers like Motorola Inc. and STMIcroelectronics have begun to migrate toward 0.35-µm and finer CMOS design rules. As these companies scale their respective bipolar-CMOS-DMOS (BCD) processes to finer geometries, they have tackled isolation problems. This has enabled them to bring both low-voltage CMOS and high-power DMOS switching circuits on the same piece of silicon, within close proximity of each other.
Copper Metallization Added As this technology evolves with scaling, new metallization schemes are being deployed. For example, to cut gate delays and improve electromigration ruggedness, dual-damascene-based copper metal interconnects are replacing traditional aluminum interconnects. In reality, though, both copper and aluminum metal layers are being incorporated in a single super-smart power device, with the top metal layers implemented in copper to handle higher currents for the power structures, and the lower layers implemented in aluminum for the lower-current logic structures.
Attempting to pack more transistors on a single chip, smart power IC developers at Motorola Semiconductor have successfully merged low-voltage microcontroller core, nonvolatile flash, and other memory types with analog and high-voltage power components on the same substrate using a 0.35-µm CMOS logic platform. This isn't a trivial task, considering the thin epitaxial process involved, which is the company's latest SMARTMOS7 process, and its limited thermal budget. According to Motorola, these hurdles were overcome by combining high-energy implantation techniques with clever doping profiles for p and n layers (Fig. 1).
In this scheme, high-energy implants are implemented in the process prior to field oxidation to realize a thick field oxide in the drift region. The advanced implantation method doesn't cause silicon damage as no major thermal steps are needed after the field oxidation flow.
"Energies of the implant chain are carefully chosen to provide adequate junction depth for a high breakdown voltage without adding any manufacturing complexity to the existing implantation process," says Bob Baird, technology manager for Motorola's SMARTMOS Technology Center.
As a result, the developers have been able to integrate a 65-V reduced-surface-field LDMOS power device, with a wide safe-operating area, into a 0.35-µm CMOS logic platform. In fact, experimental work suggests that by further adjusting the doping profiles, the new method can provide breakdown voltages as high as 88 V.
The process also offers very low RDS(on). In essence, it provides an optimum RDS(on) × area, the figure of merit for an LDMOS transistor fabricated in a deep-submicron CMOS process. Tests indicate that the figure of merit obtained for this high-voltage DMOS structure is 0.56 mΩ × cm2. Aside from providing power MOSFETS with a maximum guaranteed voltage rating of 65 V, this technology supplies low- and high-voltage analog MOSFETSs, npn and pnp bipolar transistors, linear capacitors, and a wide array of diffused and polysilicon resistors.
In essence, the SMARTMOS7 process incorporates capabilities needed for a broad range of voltage applications, from portable power management where the maximum voltage is 7 V, to high-voltage automotive applications in which 50-V capability is necessary. These results were presented at last year's International Symposium on Power Semiconductor Devices (ISPSD 2000) in Toulouse, France.
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