[Design Application]
Signal Integrity Tips Ensure FPGA Designers Meet Critical Market Windows
Early detection, use of a virtual prototype, and an ounce of prevention may be all you need to stop SI effects in their tracks.
Today, high-speed field-programmable-gate-array (FPGA) designers encounter signal-integrity (SI) issues with increasing frequency. Unfortunately, the first indication of such a problem is often a prototype that works intermittently or has an unacceptably slow clock speed. In production, yields may be low or parts could have early mortality in the field.
Why do so many high-speed FPGA designs suffer from SI problems? The answer is simply that signal edge rates are faster than ever before. The quicker the edge rate, the more likely that SI failures will occur.
Designers certainly want to prevent these failures. Ninety percent of the solution lies in identifying potential problems before the first prototype is even constructed. This is particularly true for SI problems because intermittent failures are difficult to troubleshoot on a prototype. Fortunate is the designer who performs virtual prototyping, which entails simulating SI on critical nets and boards. Because problems can be fixed during design, the number of prototype turns due to SI issues can be reduced significantly. One company went from 94% prototyping failures to less than 1% by merely implementing virtual prototyping.
Early detection of SI problems can result in large cuts in cost. Reducing the prototype turns leads to tremendous savings on board stuffing, redesign, layout revisions, and retesting. And when designs are completed more quickly, obviously products can reach the market sooner, enabling the company to reach critical market windows.
Beware of SI Effects The effects of SI are often categorized as overshoot, undershoot, and ringing on nets with fast drivers (Fig. 1). Crosstalk may appear as an overshoot or an undershoot, or it may just affect timing to the point that the logic no longer operates correctly.
Overshoot doesn't cause logic failures in most designs. Large overshoots can clear latches, though, and lead to apparent data faults. If overshoot causes clamp diodes to turn on, receivers can slow down. This results in timing problems at desired system clock speeds. Repeated large overshoots damage clamp diodes, which can end with early mortality in the field.
Ringing can make a signal go into the "no-man's land" between VIL and VIH. Because the logic threshold for an input is between these voltages, this signal is subject to misinterpretation. Consequently, a clock may appear to change state, loading data into a latch. A data line may be misinterpreted, resulting in the capture of an invalid value.
Crosstalk can lead to overshoot or undershoot on a quiescent, or non-switching, net. This is distinguishable from problems begun by SI because crosstalk results from the switching of neighboring nets, rather than the net itself. Plus, crosstalk can bring about setup-and-hold timing failures. Interactions between a switching net and its switching neighbors can lead to variations in delay of 5:1 or more (Fig. 2).
Effects Of SI And Crosstalk SI and crosstalk effects are more pronounced on longer nets. There's a critical length below which SI effects are generally tolerable. This critical length is equivalent to (1/6) × (V/TR), where TR is the signal rise time and V is the speed of the signal in the transmission line. That's 0.5 to 0.8 times the speed of light in free space. For a 1-ns edge and FR-4 (εR = 4.7), the critical length is (1/6) × [(5.5 in./ns)/1 ns], or 0.9 in. For routed nets longer than the critical length, it's usually necessary to terminate the net to reduce SI and crosstalk effects.
Many logic families have fast enough edge rates to cause SI problems. The I/O logic levels and edge rates are determined by the modules that are connected on the board, so the designer has a limited number of choices. Interface specifications operating above 50 MHz (the fastest edge rates below 2 ns) are at a higher risk. Designers who watch for fast edge rates and clock speeds and address SI early in the design have better chances at creating working prototypes.
SI and crosstalk problems are caused by dV/dt and dI/dt effects. Logic families with higher-voltage swings, such as 5-V CMOS, will experience problems at lower frequencies of 20 to 30 MHz. But critical lengths will be relatively long. Logic families with lower-voltage swings, like LVDS, will have problems only at higher edge rates, but critical lengths will be shorter. Even a 1-MHz signal can have SI problems if the driver has an edge rate of 3 V/ns.
Once the I/O specification is selected, the designer can decide to make tradeoffs between the driver characteristics and the needed additional components on the board. The driver strength and speed can be traded as well. Furthermore, they can be swapped for required termination components to achieve the desired SI. For instance, a slow, low-drive strength driver may not produce SI problems. Yet, it may be too slow in the circuit. The designer might then choose a faster edge rate or a higher drive strength. Generally, the faster driver edge rate is more likely to necessitate the adding termination components onto your board and, hence, its valuable space will be used up.
SI problems can be reduced by selecting a lower-swing logic family and the slowest-driver edge rate that's compatible with design requirements. In many applications, a slower driver with a higher drive strength is preferable to a faster driver with a lower drive strength. This has the added benefit of lowering the number of nets longer than the critical length. Long nets are most likely to require termination, so selecting a slower driver will, in turn, help reduce board area.
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