[Product Innovation]
Chip Set For Symmetric DSL Doubles Twisted Pair's Reach
The two-chip set uses advanced algorithms and an embedded MIPS processor to realize DSL's true broadband potential.
Despite the many exciting advances taking place in fixed wireless, satellite, and optical communications, the task of bringing broadband services that last mile, to the consumer, still falls on the shoulders of plain old copper lines. This copper can take the form of either coaxial cable lines, or the well-established twisted-pair lines that are taking advantage of advances in digital subscriber-line (DSL) technology
Often maligned for its limited reach, and for the need for two twisted-pair lines for high-bit-rate (HDSL) implementations, DSL has had trouble penetrating the mass market. Now Excess Bandwidth, a young startup based in Cupertino, Calif., may have found the path to DSL ubiquity, using advanced, proprietary, training algorithms for training, equalization, and echo cancellation. With support from a high-end, embedded, R4000 MIPS execution processor, the company's engineers have realized a low-cost, low-power, two-chip HDSL2/G.shdsl solution (see "Why HDSL2? It Goes The Extra Mile(s)," p. 72).
The solution comprises two chips—the EBS710-H tunable analog front end (AFE), and the EBS720 digital processing chip. Together, the chips exceed the ANSI HDSL2 specification for 1% worst-case crosstalk and bridge-tap scenarios. Thereby they double HDSL2's specified reach to 1.5 Mbits/s over 18,000 ft. of 26 AWG twisted-pair, or 24,000 ft. of 24 AWG lines. The 1.544 Mbits/s over 9000 ft., that the HDSL2 spec defines, covers up to 50% of all loops, and over 75% of business loops. The symmetrical nature of the specification allows the chip set to readily support the simultaneous data, multiple-voice, and video-conferencing technologies presently appearing.
Taking advantage of the ubiquity of the plain old telephone system's (POTS) twisted-pair infrastructure, DSL, in its various forms, has proven very successful in the face of other copper-based technologies, such as cable. Still, the ever-present demand for more bandwidth, increased services, and greater reliability, combined with the need to extend the range of DSL, has put the onus upon manufacturers to reevaluate the longevity of asymmetric DSL (ADSL). Though it's the most popular version of DSL, advanced alternatives like HDSL stand poised on the sidelines to enter the fray and pick up where ADSL leaves off.
Defined under ANSI standard T1E1.4, the latest incarnation of HDSL, called HDSL2, offers increased reach, extreme robustness and reliability, and fast, symmetrical connections that more readily support the simultaneous data, multiple-voice, and video-conferencing applications coming our way. In addition, the ITU is working on a global, more generic form of HDSL2, called G.shdsl.
While it sounds good in theory, the practicalities of implementing the HDSL2 standard have proven difficult. An extremely high noise margin has delayed the deployment of the technology as semiconductor manufacturers have struggled with issues surrounding equalization, echo cancellation, integration, and power consumption. To date there have been only a handful of implementations that have been able to meet the specification at a reasonable cost.
The level of performance is extremely difficult to attain, and requires the advanced digital signal-processing (DSP) algorithms that Excess Bandwidth has thrown at the problem. These algorithms, which are proprietary and remain under wraps, have determined the number and location of the taps required to perform the training, as well as the circuit tuning needed for optimum performance.
As a result of the increased number of taps and advanced algorithms, the amount of processing required demanded the use of an R4000, 32-bit RISC device running at 75 MIPS. This keeps the training time down to 20 to 30 s. To date, the typical solution has managed to survive by using a relatively low-end 8051 processor. But, that would be swamped by the calculations required here.
A key factor in the success of the Excess Bandwidth algorithms is the fact that they take into account the effects of both the amount and type of crosstalk present. The equalization is based on actual line measurements, and the running of an algorithm that provides for the best possible signal-to-noise ratio (SNR) at the output of the equalizer. Plus, the algorithms provide sophisticated "training" of the digital as well as the mixed-signal parts of the solution.
Training dynamically adjusts performance to the conditions of the line to which the solution is connected. This results in better overall system performance and provides a very high degree of interoperability. The end result is a system that always meets the 3.75-dB criterion, and in some cases performs to within 1 dB of the theoretical limits.
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