[Technology Report]
Leveraging Intellectual Property Gets Easier As Standards Make Headway.
Advances in the creation and "standardization" of IP allow SoC designers to better assemble complex single-chip solutions that work right the first time.
In the creation of system-on-a-chip (SoC) solutions, designers have already accepted the fact that they cannot create every functional block that gets integrated on a chip. Therefore, they must rely on outside sources to provide a number of predesigned functions required to complete their chip design. To meet those demands, there are currently well over one hundred companies, ranging from very small sole-proprietor organizations to Fortune 500 companies, offering some form of silicon intellectual property (IP) for license or sale. Until recently, such blocks carried few details with them about their testability, interfaces, and other information that could define aspects of their functionality and performance.
Formations of industry organizations like the Virtual Socket Interface Alliance (VSIA) help to set standards and guidelines for chip-oriented IP. This has contributed greatly to the improved quality of IP blocks. In addition to setting standards for various aspects of IP, the VSIA meetings serve as a forum to shed light on all of the issues surrounding the creation, use/reuse, interconnectivity, testing, and documentation requirements.
One area not heavily addressed at VSIA meetings relates to various legal issues as well as the sale/licensing aspects of the IP. Along with this comes one of the biggest cans of worms—who takes responsibility for ensuring that the IP block performs as promised on the data sheet? Is it the purview of the IP supplier, the chip foundry, the SoC designer, or some combination of all three?
To some extent, the large foundries are trying to put that issue to rest by prequalifying an IP block before it's added to their library. In a few cases, foundries have set up a rating system akin to the olympics, with gold, silver, and bronze rankings for cores. Gold typically represents cores already production proven. Silver might represent cores that, though verified, haven't yet been used in a SoC design. Lastly, bronze could represent the announced availability of a soft core that hasn't been implemented in the foundry's process.
By noting the status of the core in the IP catalogs, the foundries can forewarn designers regarding the amount of work that might be needed to integrate the core into the SoC. Both the UMC Group and TSMC, as well as LSI Logic and other foundries have such rating programs in place.
Have It Your Way Cores, megacells, and other IP building blocks are available in many forms, which makes the selection process even more challenging. The most common form in which designers obtain IP is typically the hard core.
A hard core is a physical representation of the desired function in final placed, routed, and ready-to-be-fabricated form. In essence it's a "black box" that has defined inputs, outputs, physical size, fixed functionality, and guaranteed performance specifications. Many companies offer IP blocks in this form because it provides the ability to optimize the internal workings in order to maximize performance and deliver the best performance possible.
Offering a fixed layout, though, ends up impacting other aspects of the IP usage. For instance, the fixed physical layout of the block prevents the foundry from quickly scaling the design as higher-performance processes bank on ever-decreasing feature sizes.
Hard IP is typically designed for production at a specific feature size and with specific process parameters. To move a complex function, such as an embedded processor core or memory array, to a finer-featured process often requires months to shrink, relayout, and reverify the functionality and performance. Many legacy functions, or those designs of IP blocks extracted from older chip designs, fall into this category.
Hard cores can inadvertently limit design flexibility too. The preset physical shape requires that a specific area of the chip be reserved. Additionally, depending on the number of metal layers used, there may be few or no "through-the-cell" or "over-the-cell" routing opportunities. That could cause the overall chip placement and routing tools to expand the chip to accommodate more routing space.
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