[Product Innovation]
Integrated USB 2.0 Chip Extends Its Reach To High-Speed Peripherals
This chip promises designers time-to-market and other advantages when implementing the new 480-Mbit/s standard.
For most of its young life, the Universal Serial Bus, commonly known as USB, has been relegated to the slow lane. While designers have developed USB keyboards, mice, and 56k modems, high-speed peripherals have overpowered the current USB 1.1 bus. This is about to change. The recently released USB 2.0 standard boosts speeds up to 40 times faster than the previous USB 1.1 standard. This extends the reach of USB to hard-disk drives, cable modems, home networking products, and other kinds of fast peripherals.
With the USB 2.0 standard now in place, it isn't surprising to see companies developing chips to support it. One of these companies is Cypress Semiconductor, the market leader in USB controllers. It has developed a single-chip USB 2.0 solution called the EZ-USB FX2. This chip contains a USB 2.0 physical-layer (PHY) circuit and an 8051 microcontroller based on the company's EZ-USB FX architecture.
The company believes the single-chip EZ-USB FX2 has certain advantages for designers developing USB 2.0 peripherals in comparison to both the multichip and ASIC approaches. With a multichip solution, a designer basically purchases a USB 2.0 transceiver and serial interface engine (SIE), and interfaces the transceiver to a microprocessor. In this situation, that microprocessor deals with much of the USB protocol. With a single-chip approach, which is the one that Cypress is taking with the FX2, a designer can interface the chip directly to the peripheral application.
Of course, a designer can achieve the highest level of integration by building a system-on-a-chip ASIC and integrating all of the necessary parts onto it. But then, the designer is faced with doing the work for both the application and the USB 2.0. This means the design effort is higher and time-to-market is longer. The benefit of such an approach is that the cost of the final parts can be really low. For very high volumes, this approach is definitely worthwhile. Still, Cypress believes the sweet spot is the single-chip approach and this is the reason why the company built the USB 2.0 microcontroller.
Concerning time-to-market, the company says that all of the ASIC approaches it has ever seen usually required two design spins, because doing USB protocols is a difficult job. This level of difficulty is likely to increase at 480 Mbits/s, making it a little more risky when taking the ASIC approach, particularly regarding the time-to-market.
Cypress points out that interfacing between digital and analog has more nuances when running at 480 Mbits/s. There's a lot less noise tolerance, for instance. For one thing, the voltage swings in USB 2.0 are smaller than in USB 1.1. Creating a 100-kgate IC, for example, with the small PHY is going to present a greater challenge. The company claims it isn't going to be impossible, but it will certainly affect the time-to-market. In the company's opinion, the first ASICs will have to be spun twice, which is what will affect time-to-market.
Another point Cypress makes is that the USB 2.0 protocol requires a designer to perform the initial renumeration at the USB 1.1 "full-speed" rate (12 Mbits/s). In other words, the transceiver and SIE for USB 2.0 has to do both the full-speed and the high-speed rates. This means the design must be compatible with USB 1.1 as well as USB 2.0. Cypress thinks ready-made solutions are definitely going to have an advantage over solutions done from scratch.
A Fine-Tuning Should Help Cypress believes its single-chip solution has given the company a chance to fine-tune the USB 2.0 architecture. This is a factor to consider when it comes to obtaining the high-performance I/O needed to keep up with the 480-Mbit/s USB 2.0 speed.
In addition, Cypress sees a problem with pin count in multichip solutions. In USB 1.1 devices, the data-path width was 8 bits. Now, with USB 2.0, the width is at least 32 bits for the data path. This can result in large packages, like 100- and 128-pin plastic quad flatpacks (PQFPs). According to the company, this is just for the SIE and PHYs. It doesn't include a microcontroller. The package can swamp the cost of the die. Therefore, the overall system cost can be higher.
Cypress has three versions of its chip, with the smallest a 56-pin small shrink outline package (SSOP). The reason for the low number of pins is that the wide data path is inside the chip. The package pins are for interfacing to the outside world.
In summary, the advantages of the single-chip approach can be thought of as performance, flexibility, and value. With the wide data buses inside the chip, the company can actually tune the architecture, as mentioned, to accommodate the high speed. One of the features of the FX2 part is the ability to use a low-cost microprocessor, the 8051, and still achieve very high performance. As for flexibility, programmable interfaces on the USB 2.0 part can be programmed to a specific application. Value comes from high integration and a low-pin-count package.
The FX2 features an 8-bit 8051 microprocessor core, which runs at 12, 24, or 48 MHz, depending on the application (Fig. 1). The reason the microprocessor has a wide range is to accommodate various power consumption and application needs and still maintain the high data rate of USB 2.0. In addition, the USB endpoint data buffer and slave FIFO are now one and the same FIFO. It connects directly to the Cypress Smart USB 2.0 SIE. As shown in the diagram, data can come into the transceiver, go through the SIE, and then move directly to the FIFO, which is accessible in the outside world through an 8- or 16-bit data path. Notice that there's no microprocessor in that data path.
Still, the microprocessor does have access to the FIFO. It can look at packet headers, for example, for Internet access applications. But, the speed of the data path is independent of how fast the processor is running. This is an example of the tuned architecture.
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