The Electronic Design Automation (EDA) industry continues to face new challenges as it targets ever shrinking deep-submicron geometries. Each successive advancement of semiconductor technology has brought about a new very-deep-submicron (VDSM) phenomenon, such as heat dissipation, electromigration, and interconnect coupling. Many EDA design tools have been enhanced to deal with these issues. Now another issue, circuit aging, has come to the forefront. This phenomenon must be addressed to ensure VDSM performance.
Circuit aging refers to the deterioration of circuit performance over time. The length of time can be a few years to a few months under worst-case conditions. Circuits have always aged. But, this aging wasn't significant until the latest iteration of Moore's Law, which pushed transistor channel lengths to 0.18 µm. The simultaneous use of extremely small channel lengths and higher operating frequencies has elevated circuit aging from an academic exercise to a growing, and perhaps detrimental, concern for system-on-a-chip (SoC) designs.
Circuit aging can no longer be ignored. All portions of the SoC, whether analog, digital, or memory, will be affected. These negative impacts can include slower speeds, irregular-timing characteristics, and increased power consumption. In ex-treme cases, circuit aging may even cause functional failures to occur over time.
The predominant cause of circuit aging is the degradation of individual deep-submicron transistors. This behavior, known as hot-carrier-Induced (HCI) degradation, has been extensively studied since the early 1980s. A transistor conducts when carriers are sent from one side of the transistor, known as the source, to the other side, the drain. The force that propels these carriers is called the electric field. In VDSM transistors, these electric fields become much more intense. As a result, the carriers travel much faster, leading to the increase in speed. Such speeds, however, come with a price.
The carriers have been accelerated so much and travel so fast that upon their arrival at the drain side of a transistor, they literally shatter the surrounding silicon atoms. The violent collision that occurs, called impact ionization, results in the splitting of each atom into two new carriers: one electron and one hole (Fig. 1). The longer the transistor is in operation, the greater the number of new carriers that are generated. Both HCI and circuit aging are cumulative behaviors over time.
The newly created carriers wouldn't be so bad if they didn't cause damage to the physical structure of the transistor. Unfortunately, they do cause harm. In the NMOS-type transistor, the electrons cause damage at a particular area, between the gate oxide and the silicon surface. This interface can become populated with so-called interface "states" causing the NMOS transistor to have higher threshold voltages. As a result, they produce less current which translates into slower switching speeds. The exact amount of this decrease can be quantified by measuring the newly created holes that flow out through the silicon substrate (represented by ISUB).
For PMOS transistors, the degradation mechanism is a little different. The newly created electrons are at fault once again. This time, though, they lodge and trap themselves inside the gate oxide of the transistor. Such electron-trapping causes the PMOS transistor to have lower threshold voltages. As a result, PMOS transistors will have more current than before HCI degradation. The monitor for PMOS transistors is gate current (by IGATE).
The precise amount of degradation for a transistor is a complicated function of its bias or operating conditions. Usually, a fixed amount of device degradation is assigned. The time to reach this amount is used to gauge the robustness of the technology to HCI degradation. For example, it might take five months to reach a 10% change in the drain current of a transistor. Therefore, the lifetime of the transistor would be five months. For the past 15 years, lifetimes have rapidly decreased from roughly 10 years to just a few months. This downward spiraling trend has caught the eye of many semiconductor manufacturers, and is indicative of the severity of HCI and circuit aging.
Circuit aging is an unavoidable consequence of VDSM technology. The breadth and depth of its degradation will only expand as designs use smaller transistors and operate at faster speeds. Critics have argued that lowering the level of the power supply with each successive semiconductor-technology generation will significantly lower the electric fields inside each transistor. Furthermore, they claim, this will make HCI and circuit aging disappear. But, evidence proves otherwise (Fig. 2).
Incremental drops in power-supply voltage simply aren't enough to offset the rigorous pace of Moore's Law. Electrical fields inside transistors will still increase. HCI effects will still occur. Plus, SoCs will be prone to circuit aging. Given this fact, it's important to understand why each part of the SoC design—analog, digital, and memory—will be at risk.
Traditionally, analog circuitry has been implemented with technology that's at least one to two generations behind the current, state-of-the-art digital process. With the explosion of wireless communications devices, such luxuries can no longer be afforded. Current mixed-signal designs require real-time analog-to-digital or digital-to-analog conversion, not to mention RF transceiver capability. As a result, the analog portions of the SoC are now being designed with the same short channel lengths as their digital counterparts.
Certain principles of analog design make it very susceptible to circuit aging. First, analog circuitry is constantly biased even if it isn't in active operation. This means that HCI degradation is constantly occurring as transistors are always conducting currents. Next, analog performance is more closely linked to such characteristics as gain than to drain current levels. It has been shown that while current levels might degrade only slightly, the gain can degrade significantly. Third, HCI worsens a long-time enemy of analog designs—mismatch. This occurs when identically designed devices differ from one another. Experimental studies have shown that mismatch in differential amplifiers and current mirrors (two staple components of analog designs) are enhanced by HCI degradation. They ultimately contribute to circuit performance degradation over time.
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