[Technology Report]
High-Density FPGAs Take On System ASIC Features And Performance Levels
Able to provide better system solutions, FPGAs are taking on system building blocks—SRAMs, PCI bus interfaces, CPUs, and more, to boost system throughput.
Since their introduction, field-programmable gate arrays (FPGAs) have evolved from a prototyping tool to full-fledged commodity components. As chip complexities increased, however, the performance of complex logic functions formed with programmable-logic cells hasn't kept pace with the performance demanded by leading-edge applications. That has led to today's overwhelming interest in incorporating dedicated function blocks on the same silicon as the FPGA logic. The dedicated blocks can achieve much higher operating speeds than if the functions were implemented with the FPGA's logic elements.
Complex functions, like microprocessor cores, high-end PCI interfaces (64-bit/66-MHz), and other functions that need clock rates beyond about 35 MHz, just couldn't be routinely created. The limitation hasn't been the basic performance of the gates on the FPGAs, but rather the interconnection delays encountered when synthesis and other automated tools compute the placement and routing of the circuits in the logic cells. Newer tools are doing a better job, especially if they can take the physical placement into account. A few such tools are starting to appear (see "FPGA Synthesis Tools Coming Of Age," p. 102).
Yet hand-laid out and optimized functions using the logic cells of the FPGA can achieve clock speeds of 40 to 50 MHz, while dedicated blocks integrated into the base silicon can often achieve operating speeds of 80 to 100 MHz. Meanwhile, typical top performance of complex functions using automatic tools is often limited to top operating speeds of 25 to 35 MHz. In today's performance-driven world this amounts to basically lackluster performance.
FPGA manufacturers are fighting back in several ways to improve the base performance of the logic cells, the interconnect wiring, and the tools. That will provide designers with a better starting point for functions that don't require ultimate performance.
Finer-feature processes are allowing FPGA suppliers to shrink cell areas, and pack more cells on a chip. Today, most companies are already shifting their chip production to processes that employ minimum design features of 0.18 µm. A few companies, such as Altera Corp. and Xilinx Inc, have already started to move products to processes implementing features as small as 0.13 µm.
It takes more than smaller features to solve the performance issues, though. Designers must also have the ability to interconnect the cells and minimize the delay imposed by the interconnect wiring. To provide better performance in this area, FPGA vendors have added more levels of interconnect—today's high-density FPGAs now employ as many as six or seven levels of metal interconnections. Additionally, the use of copper metallization rather than aluminum is another approach being experimented with by both Altera and Xilinx. Copper promises about a 20% or better reduction in wiring delays. That translates into at least a 20% boost in operating speed.
One area where digital FPGAs still come up short is in the interface to the "real world"—that is, the analog world. The high-performance digital processes used to fabricate FPGAs don't lend themselves easily to the creation of mixed-signal functions, like op amps, comparators, analog-to-digital and digital-to-analog converters (ADCs and DACs), and other blocks.
For such functions, designers usually add discrete analog functions and components to the board to complete the system. But, that circuitry then becomes "locked in," while the FPGA could still be reconfigured.
Two companies have attempted to solve this problem by developing programmable analog arrays. Both Lattice Semiconductor Corp. and Anadyne Microelectronics Inc. have developed single-chip solutions containing a mixture of analog building blocks. These can be interconnected with programmable elements and, therefore, form any desired interface function (see "Extending The Boundaries Of Digital Systems," p. 106).
Of all the functions that designers need on a chip, memory has been the most popular. Almost every design that engineers have to do on an FPGA may require some storage, anywhere from a few bytes to tens of thousands of bytes. But the early FPGAs were very inefficient when it came to implementing blocks of SRAM. Because many of the FPGAs are based on SRAM cells to hold the configuration data, most FPGA suppliers first found ways to use the configuration lookup-table storage as general-purpose RAM. Thus, designers could make use of larger blocks of memory—typically 16 or 32 bits per logic cell, rather than lose multiple logic cells for every bit. That significantly helped improve the memory density on SRAM-based FPGAs.
Such small lookup-table memories, however, still aren't dense enough to craft the multikilobit and multikilobyte memory blocks that are needed to support CPU caches, large register files, and high-speed data-communication buffers. Therefore, not only have SRAM-based FPGA suppliers added dedicated blocks of configurable SRAM onto the FPGA, but antifuse and flash-based FPGA suppliers have done so as well. The amount of SRAM typically scales with the size of the FPGA, but designers now have anywhere from a few kilobits to as much as 16 kbytes of dense, high-performance SRAM at their disposal to support advanced system applications.
Companies are offering basic single-port SRAM capabilities in addition to dual-port memory cells or support circuitry that allows efficient dual-port implementation. Furthermore, a few FPGA suppliers are beginning to offer content-addressable memory support for applications in networking and other systems that must perform fast matching.
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