Chip suppliers and automatic test equipment (ATE) manufacturers face a growing crisis that's likely to have a profound effect on designs: the time and cost of testing is dramatically rising to nearly uneconomical levels.
A result could be that chips ship without enough testing to meet time-to-market and time-from-purchase-order goals. That can—and has—led to performance and reliability problems in thousands of systems in the field. Or ATE manufacturers, trying to catch up, could continue to develop more sophisticated testers that cost more money, further exacerbating an already tense situation between chip and test people.
Consider what's happening. On the chip side, feature sizes shrink about 30% every three years. And, the size of chips increases approximately 12% annually while 50% or more new designs are begun each year. That's already a problem. Design productivity gaps are constantly growing larger (Fig. 1).
But furthermore, the sizes of defects that can cripple sections of a die don't shrink in proportion to the reduced feature sizes, making it easier for one defect to ruin a chip. Plus, gate delays are shorter, the number of interconnect layers are increasing, and interconnect delays are becoming dominant, reports a survey from Mentor Graphics Corp.
Device complexity also increases with proliferating system-on-a-chip (SoC) designs. The Mentor Graphics survey notes that these large-gate-count designs may contain such features as a microprocessor, buses, peripherals, ASIC sections, compiled embedded software, IP cores (hard, firm, and soft), reusable blocks, multiclock domains, multifrequency domains, PLLs and on-chip-generated clocks, multiple embedded memories, and analog and mixed-signal components. That's a tall order for electronic design automation (EDA), let alone testing.
An SoC Trend
The trend toward SoC-like design is increasing rapidly. According to Rodger W. Sykes, vice president of marketing and business development for LogicVision Inc., about 1100 designs this year will be of devices with more than 1 million gates. He claims that by 2003, it's expected that there will be 4000 such designs.
This level of complexity requires a lot of test data for ATE equipment to manage—up to 1 kbyte per gate, for example. This means that up to 1 Gbyte of test data is required for a 1-million-gate device, and up to 10 Gbytes are necessary for a 10-million-gate device.
Moreover, test times to achieve fault coverage are becoming longer. "Although running 10 million clock cycles would achieve very good fault coverage for a 1-million-gate design, testing with that many cycles would take far too long," says L.T. Wang, president and CEO of SynTest Technologies Inc. "Even a barely adequate 10,000 clock cycles would take too long," he adds. "That's because there are six million potential faults in a 1-million-gate design, in checking the ones and zeros for the two-input and one-output port per gate," Wang explains.
"And, that's not even for full fault coverage, which would take too much time," says Sykes. To cope with this increasing chip complexity, ATE vendors offer high-end digital testers costing $4 million and up, observes Sykes. "As chips get even more complex, testers will cost $10 million to $15 million in a few years," he says. "It will come to a point that it costs as much to test the silicon as it does to make it," Sykes declares. "And that's just economically unacceptable."
Also alarming is a rapidly growing "tester gap." In the next decade or so, tester accuracy will move from 200 ps to 175 ps. But chip clock rates will increase to 3 GHz (a period of 330 ps), according to Mentor Graphics. That would leave an approximately 50% margin of error between chip performance and ATE capabilities.
Not only that, yield losses on chips due to the inaccuracies of ATE equipment could rise to almost 50% in the next decade or so. A few years ago these inaccuracies were only at 10%. On new device designs, yields may be less than 20%.
If external ATE isn't fully up to the job, wouldn't it be prudent to offload some of the testing tasks onto the chip itself? This is what has been evolving under a concept called design for test (DFT). An umbrella term like EDA, DFT covers a variety of techniques to enlist the device itself in helping ease the pain of testing.
In this case, DFT includes several known and newer approaches that place various hardware and software features on-chip. These approaches include automatic test-pattern generation (ATPG), scanning in its various forms, fault simulation, and built-in-self-test (BIST), which comes in two versions called logic BIST and memory BIST.
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