[Design Application]
Choose A PLD With An Embedded Processor To Enhance Flexibility
Soft-core devices have configurable parameters that simplify and speed design.
Higher performance, shorter time-to-market, and lower manufacturing costs are all improvements that can be expected thanks to the integration of microprocessors and programmable logic devices (PLDs). On that bumpy road to ever-higher integration, microprocessors and PLDs have evolved separately, but along similar lines.
The drive for increased microprocessor performance has led to devices with wider data paths capable of handling longer instructions. On-board memory caching, better clock rates, and more efficient logic operations have increased speed. Simultaneously, processors have become more complex. To deal with that complexity, designers are using high-level languages such as C, C++, and Java. The processors often come with on-chip debugging tools, like the Background Debug Mode, Enhanced JTAG, and N-Wire, in order to support those languages.
At the same time that those microprocessor advances were occurring, improved process technology resulted in PLDs that were larger, faster, and cheaper to make. While geometries continued to shrink, the size of the die remained relatively constant, so it became practical to add more elements, such as on-board RAM. As with microprocessors, great-er integration has meant memory embedded in PLD architectures. Just as increased complexity has led to the use of higher-level languages in the design of software for microprocessors, complexity in PLDs has resulted in hardware description languages (HDLs) becoming the de facto means of developing PLD designs. PLD applications have grown larger and more intricate, resulting in on-chip debugging tools.
The parallel development of microprocessors and PLDs arises from the fact that both devices employ logical operations to solve a set of problems where, within the range of functionality of the device, the exact combination or configuration of operations changes with the user's individual application. In general, operations that require the highest performance need direct hardware implementation, while less stringent performance requirements can be met with the slower sequential functioning of a microprocessor. It should be no surprise, then, that the next logical evolutionary step is the integration of microprocessors and PLDs.
In 1999, PLD development reached a point where it was possible to design a PLD that had a soft-core processor embedded in it. Both the price and performance of this unit were on a par with board-level devices. By this quantum step in integration, performance is enhanced through the elimination of on-chip/off-chip delays. Power consumption is reduced, and the smaller die and reduced manufacturing expenses all work toward lowering overall cost.
Now, 32-bit RISC processor cores are available for programmable logic. These cores are ideal for use in many embedded systems applications because of their ability to achieve higher integration, greater flexibility, and shorter time-to-market. This is the development that enabled Altera to introduce the first soft-core RISC embedded processor optimized specifically for programmable logic.
Soft Cores Versus Hard Cores One of the considerations that a systems designer has to face when using an embedded processor PLD is whether to use a soft or a hard core. In some applications, soft-core processors, or portable logic blocks, have many advantages over hard cores. Flexibility is the main advantage, as a soft-core processor has configurable parameters that enable a variety of application needs to be met. If you buy an off-the-shelf solution, there will be tradeoffs between your design goal and what's precanned in the off-the-shelf product. You may end up paying for peripherals that you don't want, or you might wind up with larger peripherals than necessary for the specific task. In both situations, one would be wasting silicon as well as wasting money. But with a soft core, you receive and pay for only what you want.
In basic hard-core technology, the standard methodology for building configurability into hard cores is to design in the desired functionality and then use registers and multiplexers to select which functionality is used for a specific application (called run-time configurability). That is, when the system boots up, it programs the registers to provide the needed function. With soft cores, configurability is built in at compile time. So, hardware is conserved because the features that aren't going to be used won't be implemented.
The configurability of the soft core also makes it easy to implement changes, which can dramatically shorten PLD design-cycle times. For example, a USB core is used for a variety of applications where each has its own characteristics. This means that each must be configured individually. If, like in a hard core, one had to design every application separately, costs would escalate.
Configurable parameters means that a designer can make fundamental performance area tradeoffs. For example, in Altera's Nios soft-core processor, the designer can choose either a 16- or a 32-bit data width (Fig. 1). Additionally, the designer can decide whether or not to use barrel shifters, which allow multibit shifts in a single clock cycle; m-step, which is a special instruction that does the add and shift in one clock cycle; and the size of the register file, which maps interrupt routines. If an application requires a lot of multibit shifts, from a performance point of view, it would make sense to implement a barrel shifter, even though it might raise your costs and require a larger chip. On the other hand, if the application doesn't require many multibit shifts, then the barrel shifter could be eliminated to achieve a smaller, less-expensive core. This provides a degree of flexibility to how fast your processor performs for a given application, versus how much of the chip it consumes. These factors, in turn, impact cost.
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