[Design Application]
At 480 Mbits/s, Signal Integrity Becomes An Issue In USB 2.0 Designs
Packaging, board layout, and chassis grounding will all be severely impacted by these high-speed components.
USB 2.0 features a more complex and demanding specification than USB 1.0. Therefore, it has implications in packaging, board layout, and chassis grounding that go beyond the considerations for USB 1.0 designs. Additionally, USB 2.0 host, device, and hub implementations must go through compliance testing before the official USB 2.0 logo can be applied. In spite of these obstacles, developers of this advanced serial bus expect a quick migration to USB 2.0 as PC manufacturers respond to users demanding higher-performance PC-centric applications.
This migration will be aided by a new generation of high-speed silicon components that can be used in USB 2.0 designs. Still, engineers will have to hone their design skills if they wish to take advantage of the performance boost dangled before them. Because they operate with a bandwidth extending up to 480 Mbits/s, these high-speed chips require that careful attention be paid to the factors that impact signal fidelity.
While IEEE-1394 is excellent for peer-to-peer applications, PC-centric USB 1.0 applications, such as printers and scanners, can benefit from the faster performance of USB 2.0. At 480 Mbits/s, this serial bus offers data throughput that's 40 times greater than its predecessor, USB 1.0. Network and access implementations for Ethernet, xDSL, and cable modems, as well as mass storage implementations like removable hard-disk drives and backup devices, will benefit from the higher bandwidth of USB 2.0. Plus, isochronous devices, especially desktop cameras, can benefit from the increased speed.
Basically, the difference be-tween USB 1.0 and 2.0 devices is data rate. While there's little change from the user's perspective—other than higher bandwidth—manufacturers of PC and peripherals will be able to design higher-speed slave peripherals with a user-friendly interface. Furthermore, some industry experts feel that USB 2.0 might eliminate the need for some other high-bandwidth interfaces, such as SCSI adapters. That would lead to a reduced need for connectors, resulting in lower total-system cost.
Those involved in drafting the new specification were very aware of the existing user base, and compatibility was carefully considered. As a result, USB 1.1 connectors and full-speed cables can support USB 2.0 with no change. Likewise, USB 2.0 hubs and hosts will be able to detect and support low-speed and full-speed peripherals (see "USB 2.0 At A Glance," p. 158).
For the designer of USB 2.0 products, however, new design and test challenges exist, including termination networks, cable and driver impedances, and driver strengths, as well as driver rise/fall times.
Board Design Considerations USB 1.0 was a very forgiving specification. At low data rates, placement of the USB 1.0 components in relationship to clock and connectors wasn't critical. In addition, electromagnetic interference (EMI) at edge rates of 12 Mbits/s isn't particularly troublesome. But, current board-layout implementations that were convenient for USB 1.0 components may require significant redesign for USB 2.0 components. New board-routing guidelines require closer attention to attenuation, jitter budgets, package/board/chassis design, and EMI/EMC shielding.
The first thing to deal with is the device itself. It's imperative that designers know the characteristics of the USB 2.0 device being used. This helps to ensure conformance to specifications in the board layout.
The attenuation/jitter budget from silicon transmitter to silicon receiver is very tight at USB 2.0 data rates. Package pin locations, pin/wirebond impedance, and the proximity of VDD/GND pins must be taken into consideration. In the less-forgiving world of USB 2.0, the selection of a device from among competitive offerings may boil down to the best pinout.
Consider, for example, that the better-performing devices won't put high-speed pins in the corners of the package, because wirebonds are the longest in the corners. Instead, high-speed pins should be placed in the middle of one of the sides of the package where the wirebond length will be the shortest. The board designer must keep trace lengths to a minimum. Therefore, when selecting a multiport design, the best choice might be a chip where all high-speed ports are on the same side of the package. If high-speed ports are laid out one per side, then the board designer may be unpleasantly surprised as traces are laid down.
In the design of a board containing USB 2.0 functionality, the number of layers, power and ground placement, and connector placement have become significantly more critical. In USB 1.0 designs, it was possible to place the device in the middle of the board with connectors up to 8 inches away at the edge of the board (Fig. 1). But, that isn't the case with USB 2.0.
The preferred board layout for USB 2.0 is illustrated in Figure 2. As you can see, the source and connector are very near to each another. There are several other features to this layout that are important.
Match Trace Impedances At the higher data rates of USB 2.0, board layout must follow tighter rules. It's possible to perform a USB 2.0 implementation using a four-layer board. Trace impedance matching, however, is the key. Long runs increase the risk of signal degradation due to cross-coupling and noise from nearby devices. Likewise, the distance between traces must be controlled.
Running signals through vias creates an impedance change that can be significant. Even 90° corners will create problems. As data rates go up, these sharp corners can become excellent antennas, radiating energy. They also impact trace-impedance mismatching because they force additional length on one of the trace pairs.
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