[Technology Report]
SoC Co-Design Is Pushing The Limits Of Software And Hardware Simulation
Hardware and software co-design tools try to keep up as transistor count continues to rise.
System-on-a-chip (SoC) design is a hot topic, and one answer to quickly developing an SoC is to use co-design and co-verification tools. With fast time-to-market as a goal, the ability to design and test on both hardware and software sides is imperative. Delaying software development and testing until the hardware is solid is no longer an option.
A number of electronic-design-automation (EDA) vendors are pushing various approaches to co-design and co-verification, an area where new tools and new approaches abound. Hardware simulation is often required as well to get the necessary performance for simulating an SoC at a reasonable speed. This is especially true when testing software-intensive algorithms, such as new network protocols or streaming-media transport and decoding.
One alternative is to use standard SoCs that are reconfigurable (see "Reconfigurable SoCs," p. 90). The other is to use software and hardware tools that allow concurrent design of hardware and software and to utilize tools that allow simulation of hardware prior to its availability.
Co-design and co-verification tools are emerging technologies. Their actual definition can vary significantly depending upon which company is presenting information on its technology. Most agree with the basic premise that co-design involves concurrent design of hardware and software with a coordinated exchange of development changes that occur throughout the design process. This includes product specification, partitioning and repartitioning of a system's hardware and software architecture, implementation of the design for simulation purposes, including hardware/software co-verification support, plus the final system implementation in silicon.
While the tools in this space are being effectively used by small groups on new projects, proven products for large projects and large groups are only now being attempted. Many organizations are still in the midst of completing projects employing conventional development tools. But, new projects implementing co-design tools are popping up all over the place. For example, Tim Redfield, software engineer at Vanteon Corp., indicates that his company is checking out new tools in the co-design space. This consulting firm, which develops ASIC, SoC, and FPGA designs, is doing so as the new tools become almost a requirement for developing larger SoCs.
The size of SoCs is both a boon to co-design as well as a bane. As SoCs become larger, the implementation and design become more complex, making tools to simplify and manage the development tasks necessary. On the other hand, simulations slow down as complexity rises. Likewise, software is becoming a larger part of an SoC system design, further aggravating simulation overhead.
System complexity is relative. A large SoC used to be around a million transistors. Now, a large SoC is pushing four times that number.
Co-design tools help address complexity by providing a consistent design framework. This is a way to partition the design between hardware and software, and to manage changes to different parts of the design, especially the relationships between hardware and software support. Often, co-verification is part of a co-design tool or else the next step when testing a design.
Hardware and software de-sign issues aren't always in sync with each other, though. The hardware design addresses details regarding implementation, which must be supported through software device drivers. Many times, software design issues are split between enhancing performance and minimizing resource usage. Each must be complemented by the hardware and software designs. This is because the hardware has to be able to run the software at sufficient speeds to address the final product's requirements. If a designer builds the wrong hardware, then the software may run too slowly. Obviously, correct operation is equally important.
Software development tools are independent of the co-design tools. Still, this application code will be brought back into the loop for co-verification. Also, many co-design tools provide a mechanism to generate basic device drivers for use with developer-generated software.
One of the major co-design tools is Mentor Graphics' Seamless-CVE. It's implemented to create virtual hardware prototypes specifically designed to run application software. Seamless-CVE can provide partitioned, high-performance co-verification using instruction-set simulators when simulating a processor core.
Cadence's Virtual Component Co-design (VCC) is another encompassing co-design and co-verification tool. Its multilingual support includes designs based on C, C++, MatLab, and SDL, as well as the Cadence Ciertoú signal-processing work system (SPW). This tool addresses hardware/software partitioning, bus and processor loading analysis, and RTOS scheduling and resource contention. Communication refinement helps convert an abstract token-level interface description into the actual signal-level interfaces. VCC co-verification includes software simulation as well as support for Cadence's Affirma HW/SW verifier.
Various ways to address design complexity and simulation overhead exist. One method is using a higher-level specification. Register-transfer-level (RTL) system definitions are a common way to specify a design, but higher-level specification languages and tools can help. On the design side, a more powerful specification using a higher-level language allows a designer to specify a portion of the system with fewer lines of code. On the simulation side, a higher-level language lets a simulation run at a higher algorithmic level instead of at a lower-level gate or register-level simulation.
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