[Design Application]
Noise Reduction Is Crucial To Mixed-Signal ASIC Design Success
Understanding the problem and possible solutions helps designers produce ICs in which noise performance doesn't hamper functionality.
This article is the first of a two-part series. It covers internal circuits and systems. Part II will deal with floorplaning, I/O-placement, pinout, and power-stability issues.—ED
Mixed-signal IC design frequently leads to nonfunctional devices because of noise problems. Large amounts of digital noise combined with sensitive analog circuitry often results in interference noise. Further complicating things is the fact that IC noise coupling usually isn't properly modeled and simulated. This leads to devices that simulate correctly, but have functional or performance problems on silicon due to noise.
There are a number of noise-reduction techniques available. Understanding the problem as well as possible solutions will help the designer produce ICs in which noise performance doesn't hamper functionality. This article deals with noise reduction for internal circuits. After designers complete the internal workings, attention then must be paid to the placement of these circuits, the selection of pin placements, interconnects, and power, ground, and substrate concerns. These topics will be discussed in the second article of this series.
Digital transition switching is the primary cause of noise in mixed-signal devices, such as a CMOS inverter. As digital inputs transition between low and high states, the gate briefly provides a resistive short circuit between power and ground (Fig. 1). Digital rise/fall transitions also produce wide-bandwidth noise, which can couple into adjacent circuits. Considering that most ICs have a large number of gates switching under clock control, the noise can be significant.
The transients shown in Figure 1 have much of their spectral content in the higher harmonics of the clock. For a 100-MHz clock, noise above 1 GHz is common. Consequently, the spectral content of transition switching becomes an RF noise problem.
At RF, all parasitic capacitors start to become transmission paths. Additionally, interconnect inductance—metal connections, bond wires, and package lead frames—has a significant effect at these frequencies. Digital designers see this problem in the form of "ground bounce" and power-supply noise.
Digital signal integrity be-comes an issue when the magnitude of the problem exceeds about one-fourth of the power-supply voltage. Mixed-signal designers have more stringent noise and power stability requirements than do digital designers, frequently under 1 mV.
Interference noise shouldn't be confused with inherent noise or distortion. Inherent noise is due to the fundamental properties of the circuit elements. Thermal and flicker noise sources are usually orders of magnitude smaller than interference noise. Distortion is primarily a design issue, where circuits respond to signals in a nonlinear fashion.
Transmitters, or talkers, are used in this article to indicate a noise source. Receivers, or listeners, are similarly used to indicate a noise-susceptible circuit.
Two approaches to noise reduction exist. In the first, a designer addresses noise problems after IC fabrication. This method requires multiple redesign efforts as well as several trips to the wafer foundry. Redesign and refabrication costs are sizable, though. Therefore, this method usually isn't practical because of time-to-market and budget restrictions.
The other approach is to consider the noise issue as part of the design process, and include noise immunity in the original design. If performed with care, this method doesn't lead to an expanded die size.
Three factors can increase noise problems. The first is an increase in switching events, caused by a larger gate count or higher "drive-strength" gates. I/O cells are especially problematic here, due to the large currents necessary to drive external loads. Increasing clock frequency can increase noise too, because inductance of interconnects and coupling capacitance is more problematic at higher frequencies. The final factor is the reduced proximity of noise transmitters to receivers. As a result, the floor planning concepts of an IC and the noise reduction go together.
Any close proximity interconnects will have coupling capacitance. Currents are what cause magnetic fields and the consequent transformer-coupling effects. Also, adjacent bond wires can couple signals. Every circuit element is coupled to the substrate. Noise generators and potential noise receivers can be coupled through the substrate as well.
Be aware that noise generation and reception is a distributed function. Most ICs have multiple sources and receivers. Transition switching isn't just digital. Analog circuits, such as comparator outputs and oscillators, can be noise generators within analog circuits.
Due to the distributed nature of the problem, the most effective solution is often a distributed methodology. Therefore, multiple strategies to reduce both noise sources and noise sensitivity can be employed throughout the system. Noise-reduction methods can be grouped into four areas: providing a low-noise, low-impedance connection for power, ground, and substrate; making any listeners less noise sensitive; suppressing/silencing the talkers; and separating the talker/listener by either proximity separation, time separation, or frequency separation. Most techniques used for noise reduction come under one of these categories.
Probably the most valuable noise-sensitivity reduction tool is the implementation of fully differential signal processing within the IC (Fig. 2). This concept uses two signals that are opposite in polarity, and the difference between the two defines the control signal. If the signals are processed and connected as a set, then coupling noise and power/ground noise are common-mode signals. Circuits with common-mode signal rejection of 30 dB or more are common. Therefore, signal noise and immunity to power, ground, and substrate noise all benefit from using differential circuits.
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