Modern, high-speed system behavior is critically dependent on power-distribution-system (PDS) designs that deliver power well beyond 400 MHz. PDS design, however, has become too complex to do by hand. Often, this results in a PDS that's either under-designed (with excessive radiated EMI and stability problems) or over-designed (driving up system cost and complexity).
By developing a design-and-analysis strategy that looks at PDS behavior in the frequency domain, designers can ensure that their PDS implementations are both reliable and cost-efficient.
Over the past five years, the use of signal-integrity (SI) tools to predict digital switching behavior has moved from the domain of the SI guru to the desk of the mainstream design engineer. SI tools have proven valuable in identifying high-speed SI and crosstalk problems. They have also assisted in developing placement/routing strategies than can be used to minimize the chance of speed-related problems after pc-board layout.
Like all computer modeling tools, SI simulators are only as good as the data fed to them. And because SI simulation is a form of analog analysis, there will always be a margin of error involved. In fact, no two analog simulators will deliver exactly the same answer, even with the same models and the same set of input conditions. There simply are no definite answers in an analog world. The accuracy of analog analysis is based on the elements used to model the circuit and how well they represent the device's real-world behavior. That's why understanding which physical effects are modeled and what conclusions can be drawn from the simulation results are the keys to the successful use of SI tools.
All simulators make some idealized assumptions about circuit behavior simply because no simulator can model every possible physical effect. For example, there are several ways to model a length of a pc-board interconnect trace. Simple models represent only the trace characteristic impedance (Z0) and delay. Such models are said to be ideal or lossless transmission line models. A lossless trace model is usually suitable for traces with data rates under 50 million transfers/s (MT/s) and less than 12 in. long. The next level of transmission-line modeling includes the trace dc series resistance, which increases with trace length.
Since a pc-board trace isn't an ideal conductor, it exhibits a linear resistance of approximately several ohms per foot. Accurate modeling of trace dc resistance becomes important if the trace is long or the circuit is sensitive to small amounts of resistance. In high-frequency circuits, the "skin-effect" phenomenon causes high-frequency currents to concentrate along the surfaces of the trace, instead of being distributed uniformly across the cross section. Because higher frequencies constrict current to flow in a diminished cross-sectional area, trace resistance per-unit length increases with frequency. That's why for SI analysis above 200 MHz, accurate modeling of skin-effect loss is so crucial.
Some of the assumptions made during SI analysis are easily overlooked. For instance, most SI models are supplied using the I/O buffer interface specification (IBIS) standard. IBIS buffer models specify best-case and worst-case switching behavior based on specific, predetermined combinations of process, temperature, and voltage. These mixtures are contained in the IBIS model file along with the buffer's behavioral data. If any of these operating conditions are exceeded, the results of any SI or crosstalk analysis using these models are invalid.
The buffer model specifies the worst-case and best-case supply voltages at the die. If the voltage at the die drops below the worst-case voltage listed in the IBIS model, the device will respond more slowly than the worst-case response predicted by the model. Therefore, SI and crosstalk analysis rely heavily on assumptions about the adequacy of the decoupling capacitors and their ability to regulate the power delivered to the chip.
The worst-case voltages in the IBIS file are determined by the semiconductor manufacturer. There are no established procedures for determining which worst-case voltages to use. IBIS models from different vendors may have different worst-case voltage values, even though the devices operate from the same supply voltage. When multiple sets of worst-case voltages are specified, the most conservative values should apply.
Another important, idealized as-sumption made by most SI tools is that the power and ground planes behave ideally at the point where the chip attaches to the board. In such cases, the planes are modeled assuming that they can deliver infinite power in zero time. While some SI tools have provisions for modeling power/ground noise, they fail to analyze nonideal power and ground plane behavior at the board level. Instead, they confine this modeling to the power-distribution system within the package itself.
As a result, modern digital designers must juggle the discontinuity between SI/crosstalk analysis and power-system design. They have to ensure that their pc-board decoupling strategy is adequate to maintain certain minimum voltages. This must be done despite the fact that they can't rely on the SI tools to help validate the performance of the decoupling structure.
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