[Design Application]
Choosing The Right DSP For Real-Time Embedded Systems
DSP selection dramatically affects every aspect of the engineering cycle and can literally make the difference between project success and failure.
Each DSP and data-acquisition system requirement presents a unique combination of delivery, cost, packaging, and performance goals to the designer. These factors must be weighed and balanced in order to arrive at an optimum architecture and design approach. Commonly, one of the first and most critical decisions to make is choosing the appropriate DSP for the system, because this selection dramatically affects every aspect of the engineering cycle. This choice can literally make the difference between a project's success or its failure.
When picking a DSP, it's important to examine both the hardware and software factors. We will first take a look at the hardware factors involved in this decision.
External bus architectures: External buses are extremely important for supplying the DSP with two vital resources: program code and data. Depending on the processor and the application, either one or both of these may be the limiting factor or bottleneck in the design and could become even more critical than the raw computational speed of the device.
The bus architectures of three popular DSPs are listed in Table 1. They are the Analog Devices ADSP21160, and two devices from Texas Instruments (TI), the TMS320C6701 and TMS320C6203.
The C6203 is the only device with two independent 32-bit buses that can operate in parallel for simultaneous cycles on both. This is extremely useful if program code can't fit within internal program memory. One bus can be employed for external program memory fetches while the other performs external data fetches.
Because the 21160 has an external 64-bit data bus, it supports single-cycle fetches of external 64-bit data words and 48-bit instruction words, both of which would otherwise require two fetches over a 32-bit bus. As we shall see, program fetch cycles for the C6701 over a single 32-bit bus can be quite critical.
The address bus for the C6701 is limited to 24 bits, which is much more appropriate for an embedded, dedicated DSP rather than a general-purpose device with many different types of peripherals. For open-architecture, embedded, board-level DSP products, the extensive memory space of the backplane bus favors devices with at least 32 address bits.
Memory architectures: Internal memory is another important hardware factor to consider. The internal memory resources for the three processors are summarized in Table 2. The 21160 provides a generous 512 kbytes of internal RAM that can be allocated freely for either 48-bit program code, or for data words of 16, 32, or 64 bits. This memory is divided internally into two equal memory blocks that may be accessed in parallel for simultaneous program and data transfers.
The processor uses a single-instruction/multiple-data (SIMD) architecture with two identical arithmetic engines executing in parallel from a single, common instruction word. The two internal RAM banks are connected to these two CPU engines over independent data paths. This arrangement doubles the data processing throughput for many applications.
Also featured is a 32-word program cache. Once program code has been loaded into the cache, both internal RAM memory blocks are free for data fetches over the associated internal buses. In this case, two operand fetches plus an instruction fetch can all occur within a single 10-ns cycle. Each arithmetic section supports three concurrent floating-point arithmetic operations, resulting in a peak processing rate of 600 MFLOPS.
Both the C6701 and the C6203 utilize very-long-instruction-word (VLIW) engines, each with eight arithmetic elements capable of operating in parallel. Unlike the SIMD model of the 21160, every element executes its own 32-bit instruction. For this reason, the internal program memory is organized in 256-bit words (8 by 32 bits) to support the execution of these VLIW instructions once per clock cycle. For the 167-MHz C6701, six of the eight elements are floating-point units, resulting in the 1000-MFLOPS peak rating. All eight fixed-point elements of the C6203, operating at 300 MHz, produce a peak rating of 2400 MIPS.
One drawback of the C6000 family is that in order to benefit from these tremendous processing rates, program code must execute from internal memory. Otherwise, eight 32-bit instructions need to be fetched over an external 32-bit bus for each VLIW instruction. On the C6701 with only one external bus for both data and code, this can substantially reduce the processing rate.
But unlike other forms of VLIW instruction devices, the C6000 family optimizes internal program memory utilization through efficient packing of the execution word and conditional execution on every instruction. Another unique feature of the C6000 family is the program cache controller. It operates on a 128-kbyte block of program memory, not just on a few words like the 21160. Large blocks of critical routine code can be loaded into the cache by enabling the cache during the first access to external memory. This can dramatically reduce costly access to external program memory. It's one of the most critically important features of the device.
DMA engines: An important hardware resource for all DSPs is the DMA controller. This device can dramatically reduce the processing load on the processor by handling all of the significant data movement tasks.
On the 21160, the fourteen DMA channels are somewhat specialized as they're dedicated to moving data between internal RAM and specific hardware resources (Table 3). Six DMA channels are dedicated to link ports, and four are allocated for the serial ports. The remaining four channels connect to the processor's external port for accessing other processors, external memory, and external I/O peripherals. These DMA channels have excellent connectivity to the interrupt system, and they support two-dimensional DMA as well as DMA chaining for automatic linked transfers.
All four DMA channels of both C6000 devices are general purpose with the ability to move data to and from internal data memory, internal program memory, internal peripherals (such as the serial ports), and external memory and devices.
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