[Product Innovation]
100-MIPS Internet Processor Enables Ubiquitous Communications
An inexpensive, embedded, and reconfigurable device accelerates the development of communications applications.
When designing communications products, the time pressure to get your product to market is intense because there's only a narrow window of opportunity during which products become winners or losers. On top of that, you must be sure that the cost is low and that your design conforms to the latest of the constantly changing standards. Furthermore, the product has to be upgradable to protect it against the impossibly short life cycles that are presently the norm. In other words, it's engineering business as usual with its next-to-impossible tradeoffs. But maybe not, thanks to Ubicom's new IP2022 "killer" embedded controller.
Shortened from ubiquitous communications, Ubicom, is the new name for Scenix Semiconductor Inc. Founded in 1996, this company delivered its first products in 1998. Ubicom offers a line of high-speed embedded controllers (SX28/52) that are widely used in a variety of telecommunications and other applications. The company's claim to fame has been its Virtual Peripheral Modules (VPMs). These prewritten software routines implement common control and interface functions, and are stored in the controller's EEPROM/flash memory.
Ubicom's objective is to make the processor's performance high enough that users can implement hardware functions in software, thereby eliminating the need for more expensive ASICs, FPGAs, or other hardware solutions. The IP2022 is the next step in this concept, but with an increased focus on embedded Internet applications. To emphasize this focus, the communications-centric software modules that will be used with the IP2022 and future products are called "ipModules."
The IP2022, if not the fastest, is one of the fastest Internet processors available. It has a RISC-like modified Harvard architecture that runs at clock speeds up to 100 MHz. (Fig. 1). The 8-bit CPU has all of the usual instructions, including both signed and unsigned 8- by 8-multiply instructions.
Separate program and data memories permit simultaneous instruction and data accesses as well as pipelined operations with fetch, decode, execute, and write-back phases, resulting in one instruction execution per cycle. Because most instructions are a single word (except for branches that take three cycles), one instruction executes per cycle giving a performance approaching 100 MIPS. That's pretty hot for a nonDSP embedded controller.
A special feature of the CPU is an internal clock phase-locked loop (PLL). This circuit is used as a fixed 50-times frequency multiplier to boost the frequency of an external crystal. As a result 100-MHz clock is obtained from a 2-MHz crystal. The use of the lower-frequency crystal reduces EMI.
The PLL also contains programmable post-divide and predivide circuitry so that the clock frequency can be selected through software. For example, speed can be reduced under program control to minimize power consumption. Execution speed can be balanced with power consumption to optimize any given application.
The on-chip program memory consists of a 32-kword by 16-bit flash plus an 8-kword by 16-bit shadow SRAM. The flash is in-system programmable through a serial pe-ripheral interface (SPI) input. The programming voltage is a typical supply voltage of 2.5 V. No separate external programmer is needed to initially load the software or update it later as required.
The data SRAM has a capacity of 4 kwords by 8 bits and is configured as 128 special-purpose registers, 128 general-purpose registers, and 3840 bytes of generic storage space. All 256 memory registers are addressable via the instructions.
Voltage requirements for the chip are 2.3 to 2.7 V, with 2.5 V typical and 4.5 V maximum for both digital and analog circuits. I/O pin voltages may be as high as 5.7 V. Separate analog and digital power and ground pins are provided to minimize noise. Power consumption is obviously dependent on clock speed.
The IP2022 is available in a 14- by 20-mm PQFP 80-pin package with a 0.8-mm pin pitch.
Communications-Optimized I/O The I/O on the IP2022 was optimized for communications applications. It has a total of 52 I/O pins divided as seven ports designated A through G. The I/O pins can be designated as inputs or outputs as necessary. The inputs are CMOS compatible. Output pins don't require external pull-up resistors, nor are they permitted. The 4-bit port A is used for high-power outputs as it can source or sink 24 mA. This allows it to drive low-power peripheral devices, like a speaker or a relay. Timer 1 also uses these pins for I/O. Ports B through G are 8 bits each and sink or source 4 or 8 mA. Port B can be set up to accept as many as eight separate interrupts.
Additionally, Port G is used for the 8-input analog multiplexer associated with the internal analog-to-digital converter (ADC). The ADC produces a 10-bit (1/2 LSB accuracy) output. The maximum sampling rate is 48 kHz. An external reference voltage may be used as an alternative to the internal 2.5-V reference. Plus, an analog comparator is available for other analog operations. It has a 15-MHz bandwidth and a 100-mV peak-to-peak minimum input. The hysteresis is selectable.
Also included in the I/O section are the following: two 16-bit timers with extended prescalers that can be used for generic timing operations, PWM, or capture-compare operations; an 8-bit real-time timer with a programmable 16-bit prescaler; an 8-bit real-time clock counter/timer with a programmable 8-bit prescaler; and a watchdog timer with a prescaler.
Ports E and F have serializer/deserializer capability. Two pairs of 16-bit serial/parallel I/Os minimize the need for external circuitry. This is a critical feature in communications and networking applications.
The serializer/deserializer (SerDes) units support a variety of protocols, including 10Base-T Ethernet, USB, SPI, and I2C. By performing data serialization/deserialization in hardware, the CPU bandwidth needed to support serial communications is greatly reduced, especially at high band rates. Providing two units allows easy implementation of protocol conversion or bridging functions, such as creating a USB-to-10Base-T Ethernet bridge. (Fig. 2).
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