[Product Innovation]
CMOS Transceiver Chip Allows 50-Gbit/s Serial Data Transmissions
This low-power IC makes possible serial backplanes that boost the performance of Internet routers, switches, and optical networks.
Serial data communications rates keep rising as the pressure for greater bandwidth continues. Recent developments in optical-fiber communications as well as 1-Gbit/s and 10-Gbit/s Ethernet have pushed semiconductor companies to produce chips that not only keep up speed-wise, but also consolidate as much of the logic as possible. The new nPower BBT3800 transceiver from BitBlitz Communications Inc. nicely fulfills those requirements, and it achieves a new level of CMOS speed/power performance.
The BBT3800 is an eight-channel full-duplex CMOS transceiver (Fig. 1). Every channel converts 8- or 10-bit parallel data into a serial signal with a data rate of up to 3.125 Gbits/s, for an aggregate bandwidth of 50 Gbits/s. Simultaneously, serial data can be converted into parallel form on each channel.
The chip's low-power feature of just 200 mW per channel allows multiple BBT3800s to work together in parallel. For example, designers could use 20 BBT3800 chips in parallel to design a serial backplane operating at a bandwidth of 1000 Gbits/s (1 Tbit/s).
BitBlitz's patent-pending Large-Amplitude Differential Logic (LADL) CMOS enables the device to operate at the 3.125-Gbit/s level with a power consumption of approximately one-third that of conventional CMOS transceiver ICs. Total power consumption is only 1.6 W or less if the high-speed transceiver logic (HSTL) mode is employed.
Depending upon the I/O requirements, the chip operates from one or two supplies. The core runs on 1.8 V, as does the HSTL parallel I/O. But implementing a parallel stub series-terminated logic (SSTL) I/O interface requires an additional 2.5-V supply. The parallel inputs and outputs comply with the JEDEC standards for SSTL2 or HSTL.
Furthermore, the transmitter contains a 4-byte (actually 10 bits wide) first-in/first-out (FIFO) memory to correct any drift associated with the transmit clock. The FIFO compensates for temporary phase drift within the transmit data stream. Should the application require it, such as 10-Gbit Ethernet, there's an 8B/10B encoder. The serializer translates the parallel data into a serial bit stream. Also, the serial I/O is designed to match a 50-Ω stripline or microstrip transmission line.
Included in the serial receive portion of the circuitry are a patent-pending PLL-type clock-recovery circuit, a deserializer, an optional 10B/8B decoder, and a 16-byte FIFO that performs byte alignment and clock compensation. Additionally, all channels share some circuitry, such as a PLL clock synthesizer, a channel alignment unit (deskewer), and a two-pin serial management data interface I/O. The internal clock is generated at the 3.125-GHz level by using an external 156.25-MHz crystal with the internal X20 PLL multiplier. Users access the management data I/O and management data control registers by using the two-bit interface.
The serial control interface complies with the standard proposed by IEEE 802.3ae (the 10-Gbit Ethernet Standard Task Force). Like earlier versions of the Ethernet standard, the serial management interface permits access to a group of 16-bit registers that control and monitor the transceiver chip.
The registers are loaded and read serially via the management data I/O pin by a 2-MHz clock on the management data control pin. Different codes let users enable or disable the 8B/10B encoding, select the clock mode, and enable serial or parallel loopback modes to allow testing and other operations. A 5-bit address is used to select one of 32 transceiver chips to activate the management data I/O.
The BBT3800 also has built-in self-test (BIST) features. The chip supports the IEEE-1149.1 JTAG testing functions as well as a variety of boundary scan codes. Furthermore, the chip contains an internal pseudorandom binary sequence (PRBS) generator for testing.
If the self-test is activated, the parallel PRBS word is serialized and sent to the output where a bit-error-rate (BER) tester can be used. Loopback connections are easily implemented via the management data I/O to facilitate additional testing.
High-Speed Serial Backplanes The BBT3800 was designed to fit many of the newer high-speed applications, like Gigabit Ethernet switches and serial backplanes in the next generation of Internet routers, WAN/MAN optical networks, and terabit switches. One BBT3800 can be used to implement two eXtended Attachment Unit Interfaces (XAUI) being defined in the forthcoming 10-Gbit Ethernet standard. Many technical details have been defined so far, although publication of the completed and fully blessed standard isn't expected until sometime in 2002. One possible XAUI implementation is shown in Figure 2.
The Ethernet media-access controller (MAC) chip supplies 36 bits of data and clock signals to the BBT3800. This represents four bytes of data with a "k" control bit for each.
To achieve the 10-Gbit/s serial rate, the parallel input bus to the BBT3800—the eXtended Gigabit Media Independent Interface (XGMII)—must run at 312.25 MHz. That means very short (less than 5 cm) pc-board runs.
The serial outputs run at 3.125 Gbits/s. These are aggregated into the 10-Gbit/s serial signal by the optical interface. The serial outputs from the BBT3800 can drive a 50-Ω transmission line up to approximately a 50-cm length on an FR4 pc board.
The BBT3800 is also targeted at any application suggesting a serial backplane. A growing number of digital designers are turning to serial backplanes in place of today's more common parallel backplanes. Who would have thought that serial transmission would be faster than parallel transmission? Parallel data transmission is inherently faster, but only for distances of a few inches.
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