[Technology Report]
Tool Up For Alternatives To Standard ASICs
Standard-cell ASIC NREs got your eyes bulging? Check out tools and methodologies for emerging alternatives like structured ASICs and, yes, FPGAs.
Unfortunately for all of us, the electronics OEM remains in a funk. Yet design work must go on, or the industry's malaise will linger. Although some 4000 ASIC starts are projected for 2003, not all of them are going into high-volume applications, which can make it very difficult to justify standard-cell nonrecurring engineering charges (NREs).
It's no wonder that research firm Gartner/Dataquest expects only around 6% growth in the ASIC market this year but is projecting growth of over 10% for application-specific standard products (ASSPs) and over 14% for FPGAs and programmable logic devices. If you look behind the numbers and at the marketplace activity of late, it's clear that a shift is under way.
For cutting-edge IC designs, standard-cell and custom ASIC implementation is the ticket to the highest performance allowed by today's silicon fabrication processes. But given that most IC designs don't see huge unit volumes and most don't require cutting-edge performance, designers often seek different solutions for standard-cell ASIC implementation.
How you ultimately choose to implement your design is a matter of tradeoffs, of course, between expected unit volumes, performance requirements, and your market window. Once all of these are weighed, it may be that there's a better way for you to go than with a standard-cell methodology.
Currently, digital logic can be implemented through four primary methods. FPGAs are the lowest in risk but carry the highest unit costs. Gate arrays are a middle ground that has fallen from wide use, as they call for only somewhat less custom mask making than standard cell. Standard cell is the option with the highest performance and lowest unit cost (good), but it also has the longest design cycle and highest NREs (bad).
Then there's the fourth option. Quite a bit of excitement surrounds a reinvention of the gate-array concept that's emerged in the past couple of years. Known variously as platform ASICs or structured ASICs, these devices offer performance levels that are just a process generation or so behind standard-cell performance, which is good enough for a very large number of applications. For many users, structured ASICs more than make up for a small performance hit in two ways: NREs are a fraction of standard-cell costs, and turnaround times are dramatically shorter. Some vendors claim that designs can go from RTL or gate-level netlist to prototypes in as little as three weeks.
The concept behind structured ASICs is to simplify the design process by having a large array of predefined logic cells. Structured ASICs typically provide on-chip resources that are similar to those found on high-end FPGA devices. This typically includes embedded memory, I/Os, clock networks, computational blocks, IP blocks, and deterministic routing. These resources are pre-fabricated and have been physically verified to work properly under normal operating conditions to reduce design cost. The chip is completed by adding two (and sometimes only one) user-customized metal layers.
STRUCTURED ASICs In surveying some of the offerings currently on the market, one finds that generally, front-end tool flows for structured ASICs aren't all that different from the flows used for standard-cell implementations. That's good news. Design teams need not completely overhaul their front-end flows to contemplate a switch to a new implementation platform. But there are certainly considerations to be made in terms of methodologies.
With regard to the availability of EDA tools for structured ASICs, few vendors have rushed to market with offerings. Synplicity has been the most prominent by far. Recently, Magma Design Automation's announcement that it would acquire Aplus Design Technologies brings it into the mix as well. Aplus has implemented a physical planning stage that defines interconnect delays at all levels (global, semi-global, local, etc.) through mapping and placement. This timing-unified synthesis and mapping process has awareness of the design's physical implementation and is driven by the timing model defined in the physical planning stage.
It's important to understand that structured ASIC cell logic blocks are complex cells. They typically include lookup tables, storage elements, multiplexers, inverting inputs, and cascading outputs, all common in FPGAs. A custom mapper that can directly map to individual complex cells yields the best quality of results.
Why should designers consider structured or platform ASICs for their chip implementation? Again, it's a matter of tradeoffs. If you know that the ASIC you're designing will be produced in extremely large volumes, or if it needs a very large number of gates, or requires absolute best-in-class performance, then standard cell is probably the best way for you to implement it. But for mid-volume production runs, or for those without the budgets for standard-cell NREs, structured ASICs may be the answer (Fig. 1).
In many cases, the best approach to design for a given structured ASIC platform of the several on the market depends on the architecture of the platform itself. NEC Electronics' approach to a design methodology for its Instant Silicon Solution Platform (ISSP) is to leverage as much of the existing design flow and its users' experience with that flow as possible. At the same time, NEC took steps to improve on the existing cell-based front-end flow, largely through strategic partnerships with key EDA vendors. Other platform-ASIC vendors have taken this tack as well.
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