Electronic Design

  
Reprints     Printer-Friendly    Email this Article    RSS        Font Size     What's This?


[Ideas For Design]
Build an improved, simpler finite state machine

Contributing Author  |   ED Online ID #6324  |   February 23, 1998


The two improvements suggested here pertain to the “Build a Simple Finite State Machine” Idea for Design submitted by Giovanni Romeo (ELECTRONIC DESIGN, July 7, 1997, p. 149). First of all, the schematic doesn’t show a register latch on the EPROM inputs. The outputs of a 27C256 EPROM will exhibit glitches during transitions of the inputs. With the free-running clock shown in the schematic, the output register will occasionally catch these glitches. This causes state-machine failures if the inputs aren’t synchronized to the clock.

Secondly, there doesn’t seem to be much reason for this application to invent a state machine language as described in the text. The following C code implements the function described in the article (see the listing). The code is simpler to understand, and took less than an hour to write and debug. It was compiled under Borland C 3.1.


Reprints   Printer-Friendly  Email this Article  RSS    Font Size   What's This?


  • Network-On-Chip Tools Arrive for The Masses
  • Tackling System Design Challenges Through Early Verification
  • ESL Tools Take Center Stage As Designers Move Up
  • Parasitic Extraction Tool Targets Next-Generation Custom ICs
  • Synopsys Jumps Into ESL-Synthesis Pool
  • Verify Control Systems Before Committing To Hardware
  • You're Using How Many FPGAs?
  • Tool Up For The FPGA Blitz
    1) Build A Smart Battery Charger Using A Single-Transistor Circuit
    (183 views today)
    2) Hot Hands For Some Cool Rock: Motion Sensing Meets Audio Engineering
    (170 views today)
    3) GPS-Derived Grandmaster Clock Delivers Ultra-Precise Time And Frequency Sync
    (90 views today)
    4) What's All This Transimpedance Amplifier Stuff, Anyhow? (Part 1)
    (86 views today)
    5) Downconverting Mixers Lower Power Consumption While Improving Performance
    (71 views today)
    ALL TOP 20



    POST YOUR COMMENTS HERE
    Name:

    Email:
    Your Comments:

    Enter the text from the image below


    Please refresh the page if you have trouble reading this text.

    Search Electronic Design
         
      
     
    Web Seminar
    Sponsored By:
    Title: Read Pacing: A Performance Enhancing Feature of PCI Express Gen 2 Switch Devices
    Speakers: 
    Date: 07/01/08
    Register: 

    Electronic Design Europe Electronic Design China EEPN Power Electronics Auto Electronics Microwaves & RF
    Mobile Dev & Design Schematics Find Power Products Military Electronics EE Events Related Resources