Electronic Design

  
Reprints     Printer-Friendly    Email this Article    RSS        Font Size     What's This?


[Drill Deeper]
New Products: More Digital ICs/DSP
Flash Memory For Wireless Systems Accesses In 60 ns; High-Performance, Low-Power CPU Outguns Pentium M

Dave Bursky  |   ED Online ID #6443  |   November 10, 2003


Flash Memory For Wireless Systems Accesses In 60 ns
Samples of a high-speed 64-Mbit flash memory are now available with random access times of just 60 ns and burst transfer frequency of 81 MHz. The MT28F644W18 targets mobile applications, with the memory core and I/O pins all able to operate from a 1.8-V supply. The chip’s memory architecture provides additional enhancements such as a flexible 4-Mbit multipartitioned architecture, clock suspend, and a fast programming algorithm to meet the performance demands of mobile platforms. The multipartitioned architecture allows for more partitions and supports code segmentation for different applications, yielding improved efficiency. In sample quantities, the 64-Mbit flash memory costs $7.25 apiece.

Micron Technology Inc.
www.micron.com



High-Performance, Low-Power CPU Outguns Pentium M
Higher instruction efficiency and faster clock speeds let the Efficeon run applications at up to 80% faster than on previous CPUs from the developer. The next-generation TM8000 CPU will initially become available in 1-, 1.1-, 1.2-, and 1.3-GHz speed grades. At those speeds, the CPUs consume 5, 7, 12, and 14 W, respectively. The processors include a new 256-bit wide very-long-instruction-word microarchitecture along with a revamped version of the company’s code-morphing software. The software allows up to eight instructions to be executed every clock cycle. The Efficeon includes three high-speed interfaces: a 400-MHz Hypertransport bus that can transfer data at up to 1.6 Gbytes/s, a double-data-rate (400 MHz) SDRAM memory bus, and an AGP-4X graphics interface.

Transmeta Corp.
www.transmeta.com


Reprints   Printer-Friendly  Email this Article  RSS    Font Size   What's This?


  • Network-On-Chip Tools Arrive for The Masses
  • Tackling System Design Challenges Through Early Verification
  • ESL Tools Take Center Stage As Designers Move Up
  • Parasitic Extraction Tool Targets Next-Generation Custom ICs
  • Synopsys Jumps Into ESL-Synthesis Pool
  • Verify Control Systems Before Committing To Hardware
  • You're Using How Many FPGAs?
  • Tool Up For The FPGA Blitz
    1) Build A Smart Battery Charger Using A Single-Transistor Circuit
    (177 views today)
    2) Hot Hands For Some Cool Rock: Motion Sensing Meets Audio Engineering
    (168 views today)
    3) What's All This Transimpedance Amplifier Stuff, Anyhow? (Part 1)
    (88 views today)
    4) GPS-Derived Grandmaster Clock Delivers Ultra-Precise Time And Frequency Sync
    (83 views today)
    5) Downconverting Mixers Lower Power Consumption While Improving Performance
    (63 views today)
    ALL TOP 20



    POST YOUR COMMENTS HERE
    Name:

    Email:
    Your Comments:

    Enter the text from the image below


    Please refresh the page if you have trouble reading this text.

    Search Electronic Design
         
      
     
    Web Seminar
    Sponsored By:
    Title: Read Pacing: A Performance Enhancing Feature of PCI Express Gen 2 Switch Devices
    Speakers: 
    Date: 07/01/08
    Register: 

    Electronic Design Europe Electronic Design China EEPN Power Electronics Auto Electronics Microwaves & RF
    Mobile Dev & Design Schematics Find Power Products Military Electronics EE Events Related Resources