[Design View / Design Solution]
Leading-Edge Diagnostic Tools Help Ramp Up SoC Production
Design-for-testability is the order of the day, as ATE systems harness the power of scan-based techniques like embedded deterministic test.
DESIGN VIEW is the summary of the complete DESIGN SOLUTION contributed article, which begins on Page 2.
There's a direct relationship between the quickest route to volume IC production and profitability. That said, today's SoC designs demand more elaborate testing and application of more types of tests. Thus, two key factors in ramping up to volume production are how fast you can troubleshoot errors in first silicon and the speed in achieving a sufficient target process yield. Failure diagnostics plays a vital role in both of these areas.
Traditional analysis methods are less productive with technology trends such as shrinking feature sizes, and conventional instruments are too cumbersome when isolating root-cause logic failures without precision guidance. This is where expert systems can step in to help track failure trends and provide warnings when problems arise. The more automated the link between the tester, diagnositcs software, and root-cause analysis, the faster products can be ramped up to volume.
Scan technology is a key enabler of effective diagnostics. Scan cells are used instead of standard flip-flops or latches for internal sequential elements. In functional mode, the cells operate as standard flip-flops or latches. In test mode, they operate as shift registers, enabling control and observability at each sequential element. Thus, a 10-million-gate SoC may have nearly 500,000 internal control and observe points using scan technology.
This article delves into the use of automatic-test-pattern-generation (ATPG) tools in scan technology and the use of built-in self-test (BIST) methods when testing SoC memory arrays. Also discussed is logic BIST diagnostics. Stressed is the fact that electronic design automation and automatic-test-equipment vendors are partnering to develop new solutions for leading-edge design-for-test and BIST diagnostics.
HIGHLIGHTS:
How Diagnostics Work
Scan technology is key to effective diagnostics. Scan cells naturally partition the complex function and sequential nature of an SoC into small combinational blocks. ATPG tools use the failing scan cells' values to run an ATPG-based diagnosis.
Diagnostics For Memories
Memory arrays within SoCs are often tested with on-chip memory BIST controllers. These controllers can easily report failing data and addresses that don't match expected values. Many times, a separate diagnostics port running from a clock other than the system clock is required.
Logic BIST And Embedded Compression
Logic BIST is almost always based on scan technology. However, scan chains are automatically loaded with results compressed into a signature by on-chip logic. Scan chains are used when tester access is impractical or impossible. Use of logic BIST will greatly simplify tester requirements and test-program data for pass/fail testing.
Design For Test Is A Must
Without guidance from a software-based diagnostic system, traditional failure analysis methods become ineffective guesswork in the face of increasing device complexity.
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