[Engineering Feature]
Distributed Design Teams: Survival Of The Best Connected
Increasing design costs and shortened product cycles have turned globally dispersed design teams into a competitive differentiator.
If you haven't already worked on a design project with engineers based halfway around the world, it's only a matter of time.
Driven by the relentless march of Moore's Law and the need to reduce cost to complete large chip-development programs on time, multisite design teams are rapidly becoming the norm in the semiconductor industry.
In a very difficult and competitive semiconductor business climate, companies look for any advantage out there. Vertically integrated companies are virtually extinct, which has led to highly fragmented design chains. Databases are ballooning and getting more complex. At the same time, everyone is trying to shorten product development cycles.
Time-to-market demands now require more efficient, more predictable design results. Finding enough people—the right people—to create these new function blocks and make them work together, all in a timely and competitive fashion, is the perpetual challenge.
As the industry transitions from 0.18 µm to an even more demanding 0.13-µm technology, the potential for delay increases by at least a third. Only about half of the chips in the 0.13-µm process arrive within required design schedules, according to research by International Business Strategies (IBS). Of the chips that fall behind, about 50% are well behind schedule. Companies that can't beat these design rollout numbers will very likely lose out to companies that can. What's a semiconductor company to do?
ENTER DISTRIBUTED DESIGN TEAMS Hiring low-cost offshore talent is now commonplace in developing widely dispersed design teams. During the boom years of the late 1990s, everyone searched worldwide for engineers. Many were located in the U.K., Israel, and Asia. Another region, India, always a stronghold for information technology (IT), has moved more aggressively into application and software development.
"We're seeing the establishment of very large design and development teams in the lower-cost areas, particularly by the larger multinationals," says Christopher Tice, senior vice president and general manager of Cadence Systems Design's Verification Acceleration Group. "There's also a lot of work going to Israel—not to reduce development cost, but to take advantage of the work of skilled and experienced engineers."
Another trend, says Tice, is the consolidation of functions into systems-on-a-chip (SoCs)—so much so that the traditional lines between software, digital logic, analog circuits, and pc-board design are becoming more blurred.
Semiconductors are now being driven primarily by software. Typical SoCs have more software than hardware content, and the percentage of software content is growing.
"It has become far more important that you don't sample on first silicon anymore. You sample on first software," says Tice. Plus, the software teams are split off from the hardware group, often in a different location, and maybe even at a different company.
A recent study by the Gantry Group LLC, which conducts technology impact analysis for industry companies, shows that design management difficulties are increasing as SoC designs give way to even more complex mixed-signal technology.
To help make its point, it quotes Cadence Design Systems, which states that more than 20% of SoCs are mixed-signal, and projects that over 70% of all SoC products will be mixed-signal devices by 2006. The result of these convergence trends—hardware-software, digital-analog, and silicon-package-boards—requires previously separate design teams to work much more closely than before.
To accommodate the parallel development of intellectual property (IP), the design chains building these products have become multilayered networks of geographically distributed suppliers. While good in theory, Gantry says that working in different time zones can make this strategy a nightmare. But with the development of new multiteam design and development tools, design-chain performance may be the primary competitive differentiation.
"Design chains," the firm says, "have become as important, if not more so, than technology innovation, since it is the design chain's efficiency that governs time-to-market." (According to IBS, a 12-month delay can result in revenue reduction of 33%.)
COST CUTTING Clearly, cost is a key motivator in new chip design. Where designing a 0.35-µm device cost at least $2 million, the Fabless Semiconductor Association says the bill jumped to more than $13 million for 0.09-µm versions (see the figure). Willem Roelandts, chairman and CEO of Xilinx and chairman of the FSA, says these costs assume that much design and verification can be done in low labor-rate geographies.
Speaking to the International Symposium on Semiconductor Manufacturing (ISSM) recently, Roelandts noted that design and verification of complex ICs now accounts for 80% of total design cost. "Design and process costs are escalating to the point where the intended application can't support the build cost," he said. "The result is that IC vendors are having greater difficulty amortizing these costs to achieve profitability."
Enhancing, or perhaps aggravating, the process is that more companies are graduating from doing some portion of the work—say, software applications—to forming and leading large-scale design teams. In fact, Cadence put together its own distributed design project team to develop Paladium, a verification/acceleration system now being used to support remote, multi-user designers simultaneously.
The Cadence program was developed in four different sites, including San Jose and India. "Talent is critical in creating the system," notes Tice. "And as I add people to my team, I'm looking for skilled workers. But I'm also always looking at economic issues, and that's what most companies look at. You have to be cost competitive."
One of the biggest cost drivers at the moment is consumer electronics, particularly wireless applications. For example, each new generation of cellular phone and PDA (which seem to be hitting retailers' shelves at an ever increasing pace) requires a new level of complexity and functionality—all consolidated into a single-chip footprint.
Reprints
