Megagate SoC designs require a different verification strategy than designs of yore. Designs with a well planned verification methodology will get to market first. With die sizes increasing and the migration to 90-nm design rules under way, design and verification complexity is outpacing existing methodologies.
Managing verification complexity demands levels of abstraction higher than the register-transfer level (RTL). Automated verification processes are mandatory for the lower levels of abstraction. There also is a pressing need for statistical Spice analysis for design yields. This less deterministic form of verification allows for "fuzzy" variations in process, operating environment, and operating life of the end product.
Today's SoCs carry a vast amount of densely packed interconnects combined with smaller VDD supply rails. The result is more nets with noise problems. This calls for analog analysis of the impact on digital behavior, in turn requiring a combination of static and dynamic methods to unravel.
In addition to tackling verification at higher levels of abstraction, such as timed and untimed transactional models, designers will begin moving toward partitioned verification. The divide-and-conquer approach is a practical means of achieving automatic verification at the transistor level. Divide-and-conquer is enforced because the EDA world still has separate verification engines for digital and analog designers. When it comes to the power-analysis side in particular, verification tools for 90- and 65-nm processes must be able to analyze both digital HDL and analog transistor-level blocks using a combination of static and dynamic methods.
RTL design handoff continues to gain ground, replacing gate-level handoff for ASIC, customer-owned tooling (COT), and structured ASIC implementations. Front-end design planning and RTL virtual prototyping have become firmly entrenched in many system houses' design methodologies. Such flows enable designers to find and fix downstream problems before lengthy and costly synthesis and place-and-route iterations.
SoC design methodologies are moving to a platform-based, application-specific form, requiring EDA tools that incorporate application-specific design expertise. Such trends will be particularly relevant to analog and RF design because a lack of experienced designers will be quickly exposed if tools can't apply some intelligence of their own.
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