Build Complex ASICs Without ASIC Design Expertise, Expensive Tools

DESIGN VIEW is the summary of the complete DESIGN SOLUTION contributed article, which begins on Page 2.

To implement custom digital logic for system-level prototyping and qualification, OEM system designers have switched from costlier FPGAs to ASICs. However, the only ASIC option was a cell-based version. Recently, though, structured ASICs arrived as an alternative. The combination of nearly cell-based density, speed, and power consumption, coupled with low nonrecurring engineering costs, short turnaround time, and compatibility, along with existing low-cost design tools, have made structured ASICs the logical choice for applications not demanding bleeding-edge performance.

The structured ASIC architecture is based on predesigned functional blocks (logic functions, timing generators, memory, and I/O) embedded in a structured manner within the base array. The ASIC's core area consists primarily of macro blocks for implementing logic functions and a fixed amount of memory blocks. The memory blocks may be integrated in the functional macro blocks and distributed throughout the array. Or, they may be embedded separately as larger blocks in the array's core. The core may also contain specialized embedded blocks, such as timing generators.

The article discusses the issues involved in deciding between a structured versus a cell-based ASIC solution. Among the topics addressed are the investments required in terms of engineering time, CAD tools, NRE cost, and schedule.

For example, for structured ASICs, the typical turnaround time from design sign-off to prototypes is one to two weeks. The cell-based version is typically eight to 10 weeks.

It's concluded that designers have a host of advantages to consider when going to structured ASICs. Ultimately, they've opened many possibilities to improve upon current synthesis flows and techniques.

HIGHLIGHTS:
Structured Vs. Gate Array	Gate arrays use prediffused transistors to address manufacturing cycle time. With structured ASICs, the focus is on the design-cycle time and reducing the overall time from design concept to receiving parts.
Sea-Of-Macros	At the heart of a structured ASIC is a "sea-of-macros" architecture that implements the custom logic for each specific design. One macro, or a group of macros, can be used to implement logic functions throughout a structured ASIC.
Mapping Is Key	The ability to map all of the FPGA's technical aspects to the ASIC is another factor that OEM system designers must consider when contemplating alternatives for FPGA migration. Structured devices include drop-in replacements for the majority of an FPGA's special functions. A cell-based ASIC, on the other hand, may require that the designer redefine the ASIC architecture.
DFT Helps Save	Added savings in schedule, engineering support, and cost can be realized during the design-for-test (DFT) phase of the design flow. Structured ASIC products are typically developed with an architecture that encompasses predesigned DFT functions.

Full article begins on Page 2