[Design Application]
Serial Backplanes Transport Designers To The Analog Zone
Designers Must Be Prepared To Deal With Trace And Connector Impedance, Termination Techniques, And DC Balance.
The Internet has driven the bandwidth explosion in today's networks, challenging designers to keep pace with a seemingly endless thirst for bandwidth. Due to the massive amounts of data transmitted between the port cards and the core switching/routing function, the backplane of any switch/router can be the congestion point of the network. So as data rates and port counts rise, high-speed serial interconnects are migrating to the backplane. Serial-backplane architectures offer advantages in pin-count and noise reduction, hot-plug capability, and flexibility in design architecture. Serial signals can be routed on STP cable, copper traces, fiber-optic cable, or any combination of the three.
The design engineer faces new challenges, however, in the transition from the traditional parallel backplane to the high-performance serial backplane. With the ever-growing data rates of serial transmissions, the line between digital and analog signaling is blurred. Maintaining signal integrity requires paying increased attention to it in board design and component selection. Transmission-line effects, radiated signals, and jitter must all be understood and designed out. Carefully consider the critical issues of controlled-impedance traces and connectors, differential routing, termination techniques, and dc balance.
This article identifies critical serial-backplane design requirements, while pointing out some of the pitfalls commonly found in those designs. Also, various serial-backplane architectures are examined, and high-frequency design techniques are discussed. For engineers who want access to more detailed equations, references are included.
When calculating the bandwidth requirements for existing and future switches and routers, it becomes clear that the backplane's throughput must be increased. In traditional shared-media backplane architectures, like those found in mainframe computers and first-generation switches and routers, data can only be transmitted one card at a time. The remaining port cards in the switch are "blocked."
The same limitation exists in loop architectures. As port counts and bandwidth requirements increase, the parallel-backplane bus architecture becomes too wide and/or fast to be cost-effective. Serial-backplane architectures solve this problem by reducing the number of signal traces routed to the central switch.
A general rule for selecting a serial-backplane approach is to pick a total bandwidth exceeding 3.2 Gbits/s. A serial design also should be considered if the bandwidth requirements between the port card and central switch exceed 1 to 2 Gbits/s. The advantages include:
Fewer signal traces. This reduces the connector size, the connector insertion force, and the complexity of routing multiple backplane traces.
Reduction of simultaneous-switching-output (SSO) noise. The high-power, high-slew-rate parallel-bus drivers used in parallel backplanes generate large amounts of EMI and SSO noise. The differential drivers in serial-backplane designs don't suffer from these problems.
The ability to hot plug.
Serial-backplane applications in the wide-area network (WAN) include new backbone terabit switches/routers, traditional digital crossconnects, and DWDM crossconnects. In the local-area network (LAN), they comprise high-bandwidth, high-port-count ATM, Ethernet, and Fibre Channel switches. Figure 1 shows a block diagram for a serial-backplane switch/router.
The designer must make a number of tradeoffs when architecting the serial-backplane system.1 First, there's the issue of choosing either a single or multi-chassis. A single chassis (Fig. 2a) allows the use of low-cost copper traces. On the other hand, a multi-chassis (Fig. 2b) design is more expandable. But it could require a fiber-optic interconnect.
Then there's the operating frequency, which must account for the distance and bandwidth of the serial transmission path. The choice of architectures also comes into play here. A partially blocking CLOS (Fig. 3) is easily expandable and typically lower in cost, and it consumes less power. But a nonblocking architecture provides the best connectivity.
Lastly, make sure you consider the number and placement of repeater circuits. Expansion architectures may require repeater circuits to restore signal integrity.
Parallel digital crossconnects or "grooming" switches demand a serial connection between the port card and the core "grooming" switch fabric. Because the switch matrix operates on parallel data, the serial backplane requires serializer/deserializer (SerDes) devices on both the port card and the switch-fabric card.
This scenario offers key tradeoffs for the serial-backplane designer, the first of which is operating frequency. This frequency must account for the distance and bandwidth of the serial transmission path. Also take into account the SerDes integration levels, which may require single, dual, or quad SerDes devices. The switch fabric will need higher levels of integration.
Finally, the designer must select an encoding scheme for the serial data routed across the backplane. Traditionally, 8B/10B is used for its excellent dc-balance characteristics and acceptance in serial-link standards, such as Fibre Channel and Gigabit Ethernet.
Packet-switched applications reconfigure connections much more frequently than circuit-switched networks. This need for rapid reconfiguration places pressure on the designer to do the following:
Determine the optimum packet size to transit the backplane
Rapidly reconfigure the switch core to maximize switch throughput
Find a fast-acquisition phase-locked loop (PLL) if a serial-crosspoint-switch architecture is chosen. Acquisition time is the number of bit times required for the receive PLL to recover from the phase discontinuity introduced when the crosspoint is switched.
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