[Design Application]
FPGA High-Level Design Methodology Comes Into Its Own
Learn Why An HDL-Based Design Flow May Be Just The Thing For You And How To Make Sure You Choose The Right Tools.
Today, the accepted design methodology for high-level ASIC design consists of capturing design intent with a hardware description language (HDL) at the register-transfer (RTL) or behavioral level. The design is then verified with an HDL simulator and synthesized to the gates. Yet this hasn't always been the case.
Gate-level design once was typical. But when the average ASIC design passed the 10,000-gate threshold, gate-level design methodologies began to break down. And, the pressure to reduce design cycles increased. As a result, high-level design became an imperative part of maintaining competitiveness. This same trend is now repeating itself in field-programmable-gate-array (FPGA) design.
With design complexity on the rise and high-level design tools becoming more readily available, the FPGA market is poised for widespread adoption of high-level design methodologies. In fact, most analysts and industry experts agree that tens of thousands of FPGA designers will turn to high-level design methodologies in the near future. This transition stems in part from the technology advances that have taken place in the electronic-design-automation (EDA), hardware, and software industries that have occurred over the past five to 10 years.
To meet the unique requirements of FPGA designers, an effective FPGA high-level design methodology must leverage these technologies. Contrary to popular opinion, the EDA industry hasn't been waiting for FPGA designers to catch up to high-level design methods. Instead, it's been waiting for high-level design solutions to catch up to the needs of FPGA designers.
While high-level design might not be right for everyone, it's certainly easy to understand its appeal. At densities of 10,000 gates or less, it's relatively easy to visualize the functionality of an FPGA design by analyzing its schematic. But when design densities begin to surpass the 20,000, 50,000, and 100,000-plus gate-level mark, ensuring that a design will work simply by looking at the schematic becomes impossible.
HDL use allows the designer to organize and programmatically analyze highly complex designs with tools like HDL simulators. In other words, simulation-result analysis for functional design verification has replaced schematic visual inspection.
FPGA designers making the switch to a high-level design methodology enjoy some obvious benefits. First, individual designers are able to handle increased complexity by working at higher levels of abstraction and delaying implementation details to a largely automated back-end process. Second, designers can shorten cycles and improve quality by verifying functionality earlier in the design cycle, when design changes are easier and less expensive to make. These benefits also drove ASIC designers to high-level design.
Making the transition to a new design methodology is never easy. There are always obstacles on the way to adoption. The migration path to a high-level design methodology for FPGA design is no exception to the rule.
One barrier that hampers the adoption of this methodology is the common misconception that FPGA designers require significantly less functionality and features in their design software than ASIC designers. The truth is that they face the same time-to-market pressures and deadlines as their ASIC counterparts. FPGA designers will use as many features and as much functionality as is made available to them. These can include advanced debugging capabilities like data-flow analysis, complete VHDL or Verilog language coverage, or leading-edge simulation and compilation performance.
Traditionally, the tools available to FPGA designers have been newcomers or "also-rans" that didn't have the quality and functionality to compete in the ASIC design-tool market. This trend must change. Today, each component of an FPGA HDL tool suite must be a leader in its class with a clear path to increased levels of functionality equal to, or approaching that of, ASIC design tools.
Another impediment that must be overcome is the economic difference between what the ASIC designer pays for tools and what the FPGA designer can afford to pay for them. While ASIC design-seat software traditionally runs over $100,000, companies rarely spend more than $10,000 for an FPGA design seat. So, EDA vendors hoping to serve the FPGA market must be structured to field products with price/functionality ratios considerably lower than what they sell to the ASIC market.
This economic requirement seems at odds with the needed functionality and flexibility. Still, highly focused, efficient organizations are delivering these solutions today.
Providing high value in design software takes commitment to organizational efficiency on the tool vendor's part. Keeping organizations small and focused is critical to reducing overhead. Also, companies that are innovative in the areas of electronic commerce, electronic software distribution, and low-cost distribution channels can further reduce their costs and pass these savings on to customers in the form of lower prices.
Of course, finding a way to help FPGA designers make the leap to HDL-based design without missing a beat in productivity also is key to gaining acceptance. Many tool vendors have responded with simplified tools, but that's not enough. Vendors must provide training that can lead FPGA designers into increasing levels of expertise at their own pace. The combination of easy-to-use tools and adequate training will ultimately help smooth the transition.
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