Over the past decade, the escalating need for faster communications speeds have driven network infrastructures well beyond the limitations of traditional copper media. In addition, they have spurred a migration to the inherently higher bandwidths achieved through fiber optics. Optical links, running at speeds from 622 Mbits/s to 2.5 Gbits/s, have already emerged as the preferred media for campus backbone LANs, storage area networks (SANs), metropolitan area networks (MANs), and wide area networks (WANs). However, from the designers' standpoint, making the leap from 10/100BaseT speeds to 2.5-Gbit/s data rates presents a host of new design challenges.
Many of the tried-and-true basic digital design assumptions that provided ample extra margins and headroom at 10/100BaseT speeds must now be reconsidered in light of the constraints imposed by multi-gigabit data rates. Designing robust transceiver systems that can reliably deal with such high frequencies at the board-edge connector requires pushing the on-board circuitry into a whole new realm, where even relatively short traces can exhibit characteristics of analog transmission lines rather than crisp digital waveforms.
In addition, the higher frequencies show much greater susceptibility to the effects of transient noise on the board and/or to jitter in the data line. Ground and power bus isolation becomes a paramount consideration, along with careful power-supply selection criteria. And, the on-board presence of potentially noisy parallel data buses provides more layout challenges for the board designer.
Clearing The Hurdles
Successfully overcoming all of these new obstacles requires astute design decisions at both the system level and the silicon level. Not only do system engineers need to use optimal board design and layout rules to minimize noise, jitter, and interference, but they also need to leverage new semiconductor-integration options to maximize available margins and headroom.
A critical first step in effective system design is the selection of transceiver components that match your architectural design requirements. Options in the newest generation of transceiver silicon include such features as internal versus external clock recovery, built-in parity checking, and diagnostic loopback capabilities. Package size, power requirements, and component cost can vary significantly depending on the transceiver's feature set and performance capabilities, so prudent selection of transceiver silicon is required.
For example, let's look at a block diagram for a SONET STS-48/STM-16 transceiver application designed to provide a fully integrated 2.488-Gbit/s PMD layer (Fig. 1). The Sumitomo fiber-optic receiver and fiber-optic transmitter components are paired respectively with integrated demultiplexer and multiplexer devices, which provide the deserialization and serialization functions to convert between high-speed bit-serial and byte-serial data. In turn, the 311-MHz byte-serial data streams to and from these components are interfaced (via an integrated multiplexer/demultiplexer) to a bank of four PMC-Sierra PM5355 devices, each handling a 77-MHz data stream.
As will be discussed in more detail , the 2.5-GHz data and clock lines between the board-edge fiber-optic components and the multiplexer/demultiplexer chips represent critical pc-board layout challenges. In addition, the multiple 311-MHz and 77-MHz data streams can present significant noise possibilities.
Integration Benefits
Silicon-level integration of transceiver components offers the immediate benefits of sharing the cost of packaging and common reference and threshold generators, as well as opening the door to simplifying the design of complex multi-channel boards. At the silicon-level, having the transmitter multiplexer, receiver demultiplexer, and clock recovery all in the same chip set allows for on-chip implementation of closely-coupled loop-timing structures.
For instance, by wrapping the receive timing back around on the transmitter, a channel can essentially be made to look like a complete low-cost terminal to the system on the other side of the transmission link. And by migrating much of the channel-switching functionality down onto a four- to eight-channel transceiver board, designers can better leverage new high-speed system-level switching fabrics, such as serial backplane architectures, that yield improved overall throughput and lower cost per channel.
Not only does sharing the receive clock with the transmitter greatly simplify the clock and timing distribution within the system, it also allows for simple on-chip implementation of repeater timing. The matching of chip-level timing with the network's overall clock synchronization can be especially important as higher-level optical network topologies migrate toward wavelength-switched capabilities (such as wavelength division multiplexing).
From an architectural standpoint, it's beneficial to conduct chip-level switching of separate wavelength data transmissions while staying completely within the overall network's time domain. Using the same bit-synchronous timing at the chip level also enables cost-effective implementation of integrated performance monitoring on-the-fly at the repeater level.
Of course, packing all of this additional functionality onto a multichannel, board-level, transceiver module at 2.5-Gbit/s speeds pushes noise and jitter management to the forefront of design challenges. Because the requirements of Bellcore, ANSI, and ITU specifications have to be met "at the connector," designers must build in appropriate margins at every point where noise and/or jitter may contribute to the overall problem. In essence, the designer has to allow for the nonideal behavior of the electro-optics, equalizers, and other factors involved in getting the signal from the off-board media to and from the serializer/deserializer circuitry in the transceiver.
As transceiver board designs move up above OC-12 (622 Mbits/s) and on to OC-48 (2.5 Gbits/s), one key problem in controlling noise and jitter revolves around transmission-line challenges that were negligible at lower frequencies. In an OC-48 design, both the tolerance for input jitter and the acceptable jitter-transfer ratio drop off significantly as the modulation frequency increases (Fig. 2).
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