[Technology Report]
New Breed Of ASICs Melds The Best Of Two Worlds
Thanks to faster turnaround times and lower development costs than full custom ASICs, platform/structured ASICs bring stiff competition to FPGAs and ASICs.
Over the last half decade, a new class of configurable ASICs has made inroads by bridging the performance and cost gap between designs based on full custom ASICs and high-density FPGAs. Known as platform and structured ASICs, these system-on-a-chip (SOC) solutions cull some of the best aspects of both custom ASICs and FPGAs. As a result, designers have a quick time-to-market option that features lower development costs than ASICs and higher performance and often lower unit costs than FPGAs (Fig. 1).
Depending on the number of metal layers, structured/platform ASICs could require just two to six weeks to produce once the RTL description is completed. In contrast, a full ASIC design might require five or more months to produce a similar chip once the RTL is completed. High-end FPGA-based designs often require more time than structured ASICs due to extra analysis often needed for timing closure and routing.
Many designers use the terms platform and structured ASIC interchangeably, and at the most general level, the two approaches are very similar. (For an overview of designing with platform and structured ASICs, see the Basics of Design on Platform ASICs, p. 64A, this issue.)
About a dozen vendors currently offer many varieties of platform and structured ASIC solutions. They fall into several groupings, the largest of which consists of companies that provide pre-manufactured silicon customized with one or more layers of metal interconnect. Suppliers in this group include Altera (the HardCopy version of its FPGA), AMI Semiconductors (Xpress Arrays), Chip Express (CX4000 and 5000 families), eASIC (eASIC Array), Faraday Technology (a metal programmable cell array), Fujitsu (AccelArray), Lightspeed (Lightning and Luminance families), LSI Logic (RapidChip family), and NEC (ISSP series).
Another company joining the fray comes from the FPGA side. Leopard Logic has just released the Gladiator family, which combines both metal-mask and RAM-based configurable logic blocks and other resources, all on one chip. Previously, the company supplied intellectual property (IP) consisting of RAM-based configurable logic.
A second group consists of what the industry calls soft IP platforms. In this group, no silicon is premanufactured. Rather, IP blocks are selected to form a system solution minus the customer's unique logic and then prequalified. The selected and prequalified blocks are solidified as an RTL description, which can then be quickly merged with the unique RTL logic defined by the customer. Companies offering such options include Atmel, eSilicon, LSI, PalmChip, and Toshiba. These solutions permit more customization because the RTL files can be edited to delete undesired functions. Yet NRE charges are higher than they are for the pre-manufactured choices since a full mask set must be created after finalizing the RTL description.
With all of these potential solutions, the old adage "the devil is in the details" aptly applies. Although most prefabricated silicon offerings have similar collections of resources—a logic fabric to host the soft IP, dedicated IP blocks such as memories, phase-locked loops (PLLs) and/or delay-locked loops (DLLs), and various I/O ports—there are differences. In some of the more feature-rich versions, you also will find dedicated CPUs, high-speed serializer-deserializers (SERDES), and still other complex functions that make sense to embed in the silicon.
But when you start looking closer, you will find significant differences among the logic fabrics. Some will be implemented from simple gate building blocks similar to the basic gate structures found in gate arrays. Although such fabrics provide the most efficient implementation for the logic and often the best performance, they require as many as five levels of metal to define the logic. Consequently, the mask charges may be a little higher than they are for structured ASICs that need only one or two levels of metal.
A few structured-ASIC logic fabrics take an alternate approach. This method uses more-complex logic cells that are somewhat like cells used in FPGAs. These cells can be configured with just one or two levels of metal. Chips using this approach might have lower non-recurring engineering (NRE) charges. But the logic cells are less efficient from a usage point of view because some logic implementations won't use all of the logic in each cell.
Within the group of pre-manufactured silicon offerings, it's possible to further subdivide the choices into perhaps two categories: basic and advanced implementations. Basic versions pack a minimal set of resources on-chip, typically consisting of the logic fabric, some memory, some PLLs or DLLs, and standard I/O cells. These implementations are usually called structured ASICs.
The more feature-replete versions typically include embedded IP blocks that support DSP operations, CPUs for control-plane applications, multigigabit SERDES channels for high-speed communications, and/or still other large blocks of IP. Such chips are frequently categorized as platform ASICs. That's because the more-complex features may often target a specific group of applications—data communications, networking, or multimedia, for example.
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