[Design Application]
CPLDs Outshine HDLC Controllers In A Multichannel Design
Programmable Logic Handles Performance Needs While Offering Customization Not Available With Off-The-Shelf Controllers.
High-level data link control (HDLC) is one of the most enduring and fundamental standards in communications. With its roots in IBM's x.25 protocol, today it is found in a wide range of communications applications. These include leading-edge systems that use xDSL transport, frame relay, and ISDN. Because HDLC also forms the basis of Signaling System 7 (SS7), it's present in most of the worldwide telecommunications network, including cellular base stations.
A variety of HDLC controller chips are available from companies like Rockwell Semiconductor, PMC-Sierra, and Siemens. In addition, microprocessors from Motorola and AMD integrate HDLC controllers on-chip. All of these solutions strive to offer flexibility and high performance. This article describes a complex programmable-logic-device-based approach that fulfills high-performance requirements, while offering a degree of customization that's not available with off-the-shelf products.
HDLC fulfills Level 2 of the Open System Interconnect (OSI) model of communications. It includes an 8-bit begin-frame flag, a 16-bit address, an 8- or 16-bit control field, variable-length payload data, a 16- or 32-bit cyclic-redundancy-check (CRC) field, and an 8-bit end-of-frame flag. HDLC is specified in the ISO/IEC 3309 standard. It provides a convenient method of transporting packet information through a network, whether it's by x.25 transactions, Switch Virtual Circuits (SVCs) in frame relay, ISDN D-channel, call setup in a cellular base-station, or Internet Protocol (IP) on xDSL transport.
System Description The HDLC controller consists of a pulse-code-modulation (PCM) highway for the full-duplex HDLC interface, memory controller/SDRAM buffer, and peripheral-components-interconnect (PCI) interface. The interface accepts 32 full-duplex HDLC frames from a PCM highway interface, which operates at 2.048 MHz. Each channel occupies one 8-bit timeslot on the PCM highway. The SDRAM frame buffer serves as the interface point between the PCM highway and the PCI bus. The configuration registers are also stored in SDRAM. Memory controller performs arbitration between PCI and HDLC accesses and DRAM refresh.
Receive HDLC frames are processed according to the HDLC protocol, and data octets are submitted to the memory controller to be written into the SDRAM frame buffer. Receive-buffer-full and end-of-frame events generate a PCI interrupt. The host on the PCI bus then reads the interrupt status register (ISR) to determine the source channel of the received frame data. The frame buffer stores frame status and error bits, along with the receive packet data.
From data deposited by the host CPU in the SDRAM frame buffer, the HDLC transmitter creates HDLC frames. Once a buffer has been transmitted, the HDLC controller signals an interrupt. The host CPU then writes more frame data into the transmit buffers.
Using as few CPLD macrocells as possible to implement the large number of HDLC and PCI registers is a major challenge. A brute force implementation of a 32-channel, HDLC state machine and PCI configuration register space could require as many as 5000 macrocells. Normally, one would consider using a high-register-count device beyond the largest CPLDs available in the market.
Because large frame buffers are required for host CPU efficiency, however, external memory is required. This memory can also be used to store PCI configuration and HDLC state-machine information. Taking advantage of the external memory, the HDLC controller is implemented using only one state machine and CRC generator. As each channel is processed, the state and CRC of the current channel is stored in the SDRAM frame buffer. The next channel's state and CRC information is re-stored from the SDRAM.
The design takes advantage of the time-division-multiplexing (TDM) nature of the PCM data, allowing the high-speed CPLD to reuse the state-machine logic for each channel. The high-speed CPLD is also used for arbitration logic between different functional blocks. This permits the design to be realized in significantly fewer macrocells.
PCM Interface The HDLC interface consists of a PCM Transmit (PCMT), a PCM Receive (PCMR), a PCM Clock (PCMCLK), and a frame sync (PCMF) signal. PCMCLK operates at 2.048 MHz. The PCMT and PCMR signals are time-division multiplexed in a fashion commonly referred to as a PCM highway. There are 32 8-bit timeslots, numbered 0 to 31. Each timeslot repeats at a 125-µs interval. Timeslot 0 is denoted with the high-to-low transition of the PCMF signal. The PCMF signal will remain low for at least one timeslot.
Each timeslot contains one channel of HDLC traffic at 8 bits/125 µs, or 64 kbits/s. Timeslot 0 is assigned as HDLC channel 0. The rest of the timeslots are similarly assigned up to 31.
The HDLC frames that are multiplexed/demultiplexed onto the PCM highway consist of a start flag, address field, control field, variable-length data packet, frame-check sequence (FCS), and end flag. For this implementation, the address and control fields are decoded by the system software.
The flag byte (01111110) indicates both the start and the end of an HDLC frame. Zero stuffing/destuffing is performed on the HDLC packets whenever five contiguous 1 bits are transmitted/received.
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