[Design Application]
Leverage CPLD Flexibility In Customized PCI Interfaces
Designers Can Match System Needs More Closely By Building Optimized PCI Interfaces With High-Density, Complex Programmable Logic Devices.
Although developed specifically for the PC industry, the peripheral interconnect bus (PCI) tackles everything from desktop peripherals to advanced network switches. For industrial or communications systems, which often use proprietary solutions, designers don't have to maintain 100% PCI bus compliance. There, programmable logic devices (PLDs) offer tremendous flexibility, allowing designers to implement just the right combination of PCI features. The challenge, however, is to find a PLD with the performance required for full-speed PCI transactions, and enough logic capacity to handle the functions.
Historically, field-programmable gate arrays (FPGAs) have been big enough, but until recently, were too slow. On the other hand, complex PLDs (CPLDs) were fast enough, but until recently, were too small. However, over the last two years, FPGAs have speeded up, and CPLDs have grown larger, so designers have an abundance of devices from which to choose. But while both types of devices can handle a PCI implementation, the recent improvement in CPLD densities, and their intrinsic features, make them very attractive for PCI applications.
For instance, CPLD architectures are inherently good for state-machine-based designs, and many areas of a PCI design can take advantage of this. Another CPLD advantage is that performance is predictable, and remains constant throughout the design cycle. CPLDs also have abundant routing resources, so meeting a particular pinout, or using all of the logic resources available is relatively straightforward.
To show how CPLDs can be used to create a customized PCI interface, let's examine the design of a simple application that can be implemented with 128 macrocells. Larger CPLDs can also be used for PCI designs with more functionality, such as initiators or designs that incorporate more of the system logic on the chip. Soon, when CPLDs incorporate on-chip memory blocks, designers will be able to implement an entire PCI interface, including FIFO memory.
Designers must consider several issues when implementing PCI applications in programmable logic. The demands of PCI require high speed, generous routing resources, high I/O count, pinout flexibility, and a consistent-performance timing model.
Compliance with the 33-MHz PCI specification demands a set-up time no longer than 7 ns. In many implementations, especially in FPGAs, the fanout requirements for the address and data buses affect set-up time. One solution is to capture the address and data values in a register at every clock cycle, then route them to where they're needed. However, this adds a clock cycle of latency. A key advantage of CPLDs is that their performance specification doesn't depend on the fanout. So the system can maintain the 7-ns set-up requirement regardless of where the address and data bus signals go.
Next, bused signals must be driven valid between 2 and 11 ns after the clock signal. In FPGAs, many delays contribute to a signal's total clock-to-output delay. These include clock-to-Q logic paths, routing, and I/O buffer delays. Often, they can add up to more than 11 ns, which would then require a wait-state to be added to the PCI interface. However, because most CPLDs have a fixed-delay timing model, they can easily propagate an output from a register to an output pin in less than 11 ns. This is done regardless of the routing, while incorporating an entire "pass" of logic (Fig. 1). In fact, most CPLD datasheets guarantee this timing delay, typically referred to as tCO2.
Another critical requirement is that the PCI device must respond to a transaction within three clocks after the address phase. If the PCI initiator does not get a response within four clock cycles, it will abort the transaction. In fact, the PCI device can respond as early as one clock cycle. This is called a "fast-response" device. Remembering that it has to meet a 7-ns set-up time, most programmable logic implementations fall into the medium or slow (two- or three-clock-cycle response) categories. By using a CPLD, designers get performance that is both fast and predictable. Additionally, CPLDs can perform a large number of logic operations within one pass of the device (or one clock cycle).
The ability to handle high-fanout signals is yet another important characteristic. Many signals within the PCI interface must be routed to 36 or more signal nodes simultaneously. This can cause significant loading problems for most FPGAs, so some type of buffering, duplication, or special routing must be used to handle these signals. Such additional support complicates the implementation significantly. However, most CPLDs have fanout-independent routing, so routing a signal to 36 nodes is no problem. Any signal from a pin or macrocell within a CPLD can be routed to as many places as needed with no change in device performance.
With most of the baseline conditions now established, let's examine the design of a PCI target interface using a CPLD containing 128 macrocells (in this case a Cypress Ultra 37128). This version can hold the smallest possible PCI target design, and allows engineers to craft a cost-effective solution while maintaining high performance and flexibility.
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