The rise of affordable microprocessors has resulted in an immense amount of computing capacity in mainstream digital design. To drive these complex devices, software has dramatically grown in size, with elaborate interface logic, usually captured in large ASICs, required to support the intricate communications between the CPU and the surrounding hardware. This growth in software and hardware complexity is straining existing design practices—especially system verification. System verification now accounts for more than 40% of the overall design cycle, an unacceptable situation given the ever-shrinking market windows. And yet, verification is the crucial factor in maximizing the likelihood of first-time success.
Until recently, the only really viable hardware/software (HW/SW) integration strategy was to bring the two components together after the hardware was built and prototyped. True, limited ways were available to merge a system's hardware and software before physical integration, but they were just that, limited. For example, hardware teams at Northern Telecom tried to model their designs using a set of component models and their connectivity, while a bus-functional model represented the microprocessor or controller.
A bus-functional model, however, does not model the microprocessor's complete behavior, only the different bus cycles the processor can execute. Using these models, the hardware designers constructed a test that would, for example, write to and then read from each of the memory components in the design. Clearly, this fell far short of what was needed for comprehensive verification.
On the software side, the teams required a fully functional model of the processor to execute software on a simulated design. However, writing a program that completely emulates the behavior of a complex processor is an extremely complex task. To obtain this model, the software team might use a device called a hardware modeler. This is a machine that contains much of the circuitry of a semiconductor tester, and is interfaced to a hardware simulator. Modeling the processor in this manner usually results in speeds of 1 to 10 instructions per second on the simulated design, which is obviously much too slow to execute and verify a meaningful amount of software.
The only realistic alternative for system integration was to wait for the hardware prototype. Unfortunately though, delaying integration that long doesn't give a design team much time to address the numerous performance issues that usually surface. Fearful of missing critical delivery dates, the temptation is to fix hardware problems in the software, leading to compromised functionality or performance goals. Consequently, Northern Telecom, like many other design teams, has been actively exploring new ways for validating system design.
Deciding To Coverify What became painfully obvious was that to fix system problems without incurring the time and expense of changing the hardware, the problems had to be discovered prior to the hardware-prototype stage. In other words, the software must be run on the hardware while it is still in simulation, as a virtual prototype.
This has been the dream for years, but two things were necessary before virtual prototyping could become a reality. First, the ability to simulate hardware at speeds sufficient to make software execution feasible was absolutely necessary. In most cases, this means that overall simulation performance must be increased by a factor of at least 1000 over the current execution speeds of hardware-oriented simulation products. Second, the debugging and development environments for the hardware and software need to be brought closer together. As a result, the original source form for both the software and hardware must be maintained within a single, unified debugging environment.
In the past few years, the underlying technology to support a true coverification environment has emerged and matured. Commercial solutions for coverification are now finally available that enable HW/SW integration earlier in the design cycle. Because these approaches create a virtual test and integration environment, software and hardware teams can now work together from the beginning. This eliminates time-consuming back-end integration and testing, helping designers to uncover problems earlier in the design process where they are less costly and easier to fix.
Moreover, due to the design's fluid nature at this stage, functional changes can be made where they make the most sense, either in hardware or software. Although HW/SW coverification technology and methods are relatively new for embedded systems designers, it is rapidly becoming an integral part of mainstream electronic system design.
Eager to adopt coverification in its design flow, the Northern Telecom design team decided to test the viability of HW/SW coverification using an embedded, digital-phase-locked-loop (DPLL) design targeted at switching applications. The decision was influenced by the software group's strong need to have access to hardware earlier in the design cycle, to test and adjust complicated algorithms, control constant determination, verify HW/SW interfaces, and conduct performance modeling. To evaluate the HW/SW interface of the DPLL design and the DPLL software algorithm within a coverification environment, the design team used the Seamless Co-Verification Environment (CVE) from Mentor Graphics.
The DPLL design was selected because it was relatively simple, yet still proved the concept. While the hardware content of this subsystem is relatively small, the software aspect is key to providing clock synchronization within a complex telecom switching environment. This design had already been created using the traditional approach; designing the hardware and software in tandem, and integrating the two only after a hardware prototype was available. Using a preexisting design to validate the coverification solution would afford the opportunity to directly compare the effectiveness of the two approaches, providing a "proof of concept."
Using the traditional approach, after the hardware team sends an ASIC design off to be manufactured, it might be as long as 11 weeks before the software team could have access to the ASIC prototype. With coverification however, the software group calculated it would obtain access up to nine weeks in advance of the traditional methodology. This is even more impressive considering that approximately two weeks of preparation was required to ready the design for Seamless, as no Verilog netlist was available from the board schematic database.
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